Avalon-St Single-Device Configuration - Intel Agilex Configuration User Manual

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09

3.1.5. Avalon-ST Single-Device Configuration

Figure 13. Connections for Avalon-ST x8 Single-Device Configuration
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External Host
CPLD / FPGA
fpga_nconfig
fpga_nstatus
fpga_conf_done
Parallel Flash Loader II IP
or
Microprocessor
or
Custom Logic
fpga_data [7:0]
fpga_valid
fpga_ready
fpga_clk
Compact Flash Interface
ADDR DATA Control
External Compact Flash Memory
.rbf
(little endian)
V
CCIO_SDM
V
Configuration
CCIO_SDM
Control Signals
10kΩ
10kΩ
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
OSC_CLK_1
(1) (2)
3
MSEL
MSEL[2:0]
8
AVSTx8_DATA [7:0]
AVSTx8_VALID
AVSTx8_READY
AVSTx8_CLK
Configuration
Data Signals
External Clock Source (Optional)
Intel FPGA
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