External I/O Termination; True Differential Signaling I/O Standard Oct Termination - Intel Agilex User Manual

3.1.1. External I/O Termination

Use AC coupling and external voltage bias circuitry if the common-mode voltage of the
output buffer does not match the differential receiver input common-mode voltage.
For information about the V
Note: Intel recommends that you use SPICE models to verify your AC/DC-coupled
termination.
Figure 7. AC-Coupled External Termination
True DIfferential
Transmitter
3.1.2. 1.5 V True Differential Signaling I/O Standard OCT Termination
All I/O pins and dedicated clock input pins in Intel Agilex devices support on-chip
differential termination, R
chip differential termination option on each differential receiver channel for 1.5 V True
Differential Signaling I/O standards.
Figure 8. OCT for Differential I/O Termination
3.1.2.1. Differential Input R
For interfaces which require external voltage bias circuitry near the Intel Agilex
device's true differential receiver, you must disable the OCT R
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
20
specification, refer to the device data sheet.
ICM
0.1 µF
Z = 50 Ω
0
0.1 µF
Z = 50 Ω
0
OCT. The Intel Agilex devices provide a 100 ±40 Ω, on-
D
Differential
Transmitter
Z = 50 Ω
0
Z = 50 Ω
0
OCT Restrictions and Guidelines
D
3. Intel Agilex I/O Termination
UG-20214 | 2019.04.02
V
ICM
50 Ω
50 Ω
Differential Receiver
with On-Chip 100 Ω
Termination
R
D
.
D
True DIfferential
Receiver
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