Intel Agilex Gpio Banks, Serdes, And Dpa Locations - Intel Agilex User Manual

5.1.2. Intel Agilex GPIO Banks, SERDES, and DPA Locations

The I/O banks are located at the top and bottom I/O rows respectively. Each I/O bank
contains two I/O sub-banks and each I/O sub-bank contains its own PLL, dynamic
phase alignment (DPA), and SERDES circuitry blocks.
Figure 23. I/O Bank Structure with I/O PLL, DPA, and SERDES (Bottom View)
This figure shows an example of I/O banks in Intel Agilex AGF 012 and AGF 014 devices. The I/O banks
availability and locations vary among Intel Agilex devices.
HPS
HPS
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
38
Top I/O bank Row
3D 3C 3B
3A
2D 2C 2B 2A SDM
Bottom I/O bank Row
Top I/O bank Row
3D 3C 3B 3A
2D 2C 2B 2A
SDM
Bottom I/O bank Row
SDM Shared HPS Shared
GPIO Bank GPIO Bank
GPIO Bank SDM I/O Bank
HPS I/O Bank
Different device packages have a different number of I/O banks. Refer to the device pin-out files for available bank location for each device package.
5. Intel Agilex High-Speed SERDES I/O Architecture
I/O Center
OCT
I/O PLL
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL
OCT
I/O Center
I/O Center
OCT
I/O PLL
I/O VR
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL I/O VR
OCT
I/O Center
UG-20214 | 2019.04.02
I/O VR
I/O Lane
I/O Lane
I/O Lane I/O Lane
I/O VR
I/O Lane I/O Lane
I/O Lane I/O Lane
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