Document Revision History For The Intel Agilex Configuration User Guide - Intel Agilex Configuration User Manual

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UG-20205 | 2019.10.09
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8. Document Revision History for the Intel Agilex Configuration User Guide

Document Version
Intel Quartus
Prime Version
2019.10.09
2019.09.30
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks
of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel
assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
19.3
Made the following changes:
Corrected definition of
Added E-Tile Transceivers May Fail To Configure to the Debugging chapter.
Revised the Modifying the List of Application Images topic.
19.3
Made the following changes to the device and software:
Added the optional
nCATTRIP
than 125° C.
Added the an eighth word to the to the
Added new field to the 5th word of the
Added
to the available operation commands.
RSU_NOTIFY
Changed the number of images that the Programming File Generator supports from 3 to 7.
Removed write restrictions for lower addresses in flash memory. (The device firmware must still reside at address 0x0.)
Made the following changes to the user guide:
Added many topics showing how to implement in the Intel Quartus Prime Pro Edition Software.
Changed the err status pulse range from 1 ms ±50% to 0.5 ms to 10 ms.
Removed the SDM Firmware state from the Intel Intel Agilex FPGA Configuration Flow diagram. This state is part of the
FPGA Configuration state.
Updated recommendations on how to debug a corrupt configuration bitstream for the AS x4 configuration scheme in the
Debugging Guidelines for the AS Configuration Scheme topic.
Corrected the signal name in The AVST_READY Signal topic: The device can starting sending data when
asserts.
Added note that the Avalon ST x32 configuration scheme is limited to 3, DDR x72 DDR external memory interfaces. The
Avalon ST x8 and x16 configuration schemes can support up to 4, x72 DDR external memory interfaces.
Corrected the Pin Type in the Required Configuration Signals for the Avalon-ST Configuration Scheme table.
is an SDM I/O pin.
AVSTx8_READY
Corrected minor errors and typos.
Changes
command. This command has 9, not 10 words.
RSU_STATUS
(catastrophic trip) SDM I/O signal. This signal asserts when the core temperature is greater
response: Word 8: Current image retry counter.
RSU_STATUS
response. This field specifies the source of a reported error.
RSU_STATUS
is a GPIO or Dual-Purpose pin.
AVST_READY
AVST_READY
continued...
ISO
9001:2015
Registered

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