Additional Clock Requirements For Transceivers, Hps, Pcie, And Emif - Intel Agilex Configuration User Manual

2. Intel Agilex Configuration Details
UG-20205 | 2019.04.03
Figure 7. Intel Agilex Reset Release IP nINIT_DONE External Connection

2.4. Additional Clock Requirements for Transceivers, HPS, PCIe, and EMIF

The Intel Agilex device has additional clock requirements for transceivers, the HPS, PCIe, and External Memory Interface
(EMIF) IP.
For successful configuration, the Intel Agilex device requires additional clocks for transceivers, the HPS, PCIe, and EMIF IP.
You must provide a free-running, stable reference clock to these blocks before configuration begins. This reference clock is in
addition to the configuration clock requirements for an internal or external oscillator described in
on page 32.
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OSC_CLK_1 Requirements
Intel ® Agilex ™ Configuration User Guide
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