Multiple Floating-Point Variable Dsp Blocks Functions - Intel Agilex User Manual

3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Figure 38. FP16 Vector Three Mode
accumulate
fp32_adder_a[31:0]
fp16_mult_top_a[15:0]
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
fp16_mult_bot_b[15:0]

3.2.3. Multiple Floating-Point Variable DSP Blocks Functions

Two or more floating-point DSP blocks can perform the following:
• Multiply-add or multiply-subtract mode which uses single floating-point arithmetic
DSP if the chainin parameter is turn off
• Direct vector dot product
• Complex multiplication
3.2.3.1. Multiply-Add or Multiply-Subtract Mode
This mode performs floating-point multiplication followed by floating-point addition or
floating-point subtraction. The chainin parameter allows you to enable a multiple-chain
mode.
Table 22. Equations Applied to Multiply-Add or Multiply-Subtract Mode
Chainin Parameter
Disable
Enable
The floating-point multiply-adder or multiply-subtract mode supports the following
exception flags:
•
fp32_mult_invalid
•
fp32_mult_inexact
•
fp32_mult_overflow
•
fp32_mult_underflow
•
fp32_adder_invalid
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Input
Register
Bank
Top
*Pipeline
*Pipeline
Multiplier
Register
Register
Bottom
Multiplier
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
Multiply-Add Mode
fp32_result =
(fp32_mult_a*fp32_mult_b) +
fp32_adder_a
fp32_result =
(fp32_mult_a*fp32_mult_b) +
fp32_chainin
*Pipeline *Pipeline
*Pipeline
Register Register
Register
Adder
Adder
*Pipeline Register
Register
fp32_chainout[31:0]
fp32_result =
(fp32_mult_a*fp32_mult_b) -
fp32_adder_a
fp32_result =
(fp32_mult_a*fp32_mult_b) -
fp32_chainin
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
Output
fp32_result[31:0]
fp16_mult_top_invalid
Register
fp16_mult_top_inexact
Bank
fp16_mult_top_overflow
fp16_mult_top_underflow
fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
fp16_mult_bot_invalid
fp16_mult_bot_inexact
fp16_mult_bot_overflow
fp16_mult_bot_underflow
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Multiply-Subtract Mode
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