Table Of Contents - Intel Agilex User Manual

Contents
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1. Intel Agilex General Purpose I/O and LVDS SERDES Overview................................... 4
1.1. Intel Agilex I/O and Differential I/O Buffers............................................................... 4
1.2. Package Selection and I/O Vertical Migration Support................................................. 5
1.3. I/O Banks.............................................................................................................5
2. Intel Agilex I/O Features and Usage...............................................................................8
2.1. GPIO Features.......................................................................................................8
2.1.1. Supported I/O Standards............................................................................ 8
2.1.2. Intel Agilex I/O Buffer Behavior................................................................. 10
2.1.3. I/O Standards Restrictions and Implementation Guidelines............................ 10
2.2. Programmable I/O Element (IOE) Features in Intel Agilex Devices.............................. 11
2.2.1. Programmable Output Slew Rate Control.....................................................15
2.2.2. Programmable IOE Delay.......................................................................... 15
2.2.3. Programmable Open-Drain Output..............................................................15
2.2.4. Programmable Bus Hold............................................................................16
2.2.5. Programmable Pull-Up Resistor.................................................................. 16
2.2.6. Programmable Pre-Emphasis..................................................................... 16
2.2.7. Programmable De-Emphasis......................................................................17
2.2.8. Programmable Differential Output Voltage................................................... 18
3. Intel Agilex I/O Termination........................................................................................ 19
3.1. 1.5 V True Differential Signaling I/O Termination...................................................... 19
3.1.1. External I/O Termination...........................................................................20
3.1.2. 1.5 V True Differential Signaling I/O Standard OCT Termination......................20
3.2. Single-Ended I/O Termination in Intel Agilex Devices................................................ 21
3.2.1. Single-Ended I/O Standard OCT Termination................................................21
3.2.2. OCT Calibration Block............................................................................... 25
3.2.3. Single-Ended I/O Standards External Termination ........................................26
4. Intel Agilex I/O Design Guidelines............................................................................... 29
4.1. Placement Requirements.......................................................................................29
4.2. Special Pins Requirement...................................................................................... 29
4.3. External Memory Interface Pin Placement Requirements............................................30
4.4. HPS Shared I/O Requirements............................................................................... 31
4.5. SDM Shared I/O Requirements.............................................................................. 31
4.6. Configuration Pins................................................................................................31
4.7. Unused Pins........................................................................................................ 31
4.8. Guidelines for GPIO Pins During Power Sequencing...................................................32
4.9. Maximum DC Current Restrictions.......................................................................... 32
4.10. 1.2 V I/O Interface Voltage Level Compatibility...................................................... 32
4.11. I/O Simulation................................................................................................... 34
4.11.1. HSPICE Models...................................................................................... 34
5. Intel Agilex High-Speed SERDES I/O Architecture........................................................ 35
5.1. Intel Agilex High-Speed SERDES I/O Overview.........................................................35
5.1.1. High-Speed SERDES Architecture............................................................... 35
5.1.2. Intel Agilex GPIO Banks, SERDES, and DPA Locations................................... 38
5.2. Intel Agilex LVDS SERDES Transmitter.................................................................... 39
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
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