Table Of Contents - Intel Agilex User Manual

Contents
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1. Intel Agilex Clocking and PLL Overview...................................................................... 3
1.1. Clock Networks Overview........................................................................................3
1.2. PLLs Overview.......................................................................................................3
2. Intel Agilex Clocking and PLL Architecture and Features................................................ 4
2.1. Clock Networks Architecture and Features.................................................................4
2.1.1. Clock Network Architecture......................................................................... 4
2.1.2. Clock Resources........................................................................................ 6
2.1.3. Clock Control Features................................................................................6
2.2. PLLs Architecture and Features................................................................................ 9
2.2.1. PLL Features............................................................................................. 9
2.2.2. PLL Usage............................................................................................... 10
2.2.3. PLL Locations.......................................................................................... 10
2.2.4. PLL Architecture.......................................................................................11
2.2.5. PLL Control Signals.................................................................................. 11
2.2.6. PLL Feedback Modes.................................................................................12
2.2.7. Clock Multiplication and Division.................................................................17
2.2.8. Programmable Phase Shift........................................................................ 18
2.2.9. Programmable Duty Cycle......................................................................... 18
2.2.10. PLL Cascading........................................................................................18
2.2.11. PLL Input Clock Switchover......................................................................19
2.2.12. PLL Reconfiguration and Dynamic Phase Shift.............................................24
2.2.13. PLL Calibration.......................................................................................24
3. Intel Agilex Clocking and PLL Design Considerations.................................................... 26
3.1. Guideline: Clock Switchover.................................................................................. 26
3.2. Guideline: Timing Closure..................................................................................... 27
3.3. Guideline: Resetting the PLL..................................................................................27
3.4. Guideline: Configuration Constraints.......................................................................28
4. Document Revision History for the Intel Agilex Clocking and PLL User Guide............... 29
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Intel Agilex Clocking and PLL User Guide
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