As Configuration - Intel Agilex Configuration User Manual

3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
Pin
flash_nreset
fpga_nconfig
pfl_reset_watchdog
pfl_watchdog_error
Related Information
Avalon Interface Specifications

3.2. AS Configuration

In AS configuration schemes, the SDM block in the Intel Agilex device controls the configuration process and interfaces. The
serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot
ROM. Then, the SDM loads the initial configuration firmware from AS x4 flash. After the configuration firmware loads, this
firmware controls the remainder of the configuration process, including I/O configuration and FPGA core configuration.
Designs including an HPS, can use the HPS to access serial flash memory after the initial configuration.
Note: The serial flash configuration device must be fully powered up at the same time or before ramping up V
Agilex device.
The AS configuration scheme supports AS x4 (4-bit data width) mode only.
Table 17. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Mode
Active Active Serial (AS)
Send Feedback
Type Weak Pull-Up
Output —
Open Drain Output 10-kW Pull-Up
Resistor
Input —
Output —
Data Width (bits) Max Clock Rate
4
Function
Connects to the reset pin of the flash memory device. A low signal resets
the flash memory device.
Connects to the pin of the FPGA. A low pulse resets the FPGA
nCONFIG
and initiates configuration. These pins are not available for the flash
programming option in the PFL II IP core.
A switch signal to reset the watchdog timer before the watchdog timer
times out. To reset the watchdog timer hold the signal high or low for at
least two clock cycles.
pfl_clk
When high indicates an error condition to the watchdog timer.
Max Data Rate
133 MHz 532 Mbps
Intel
(9)
of the Intel
CCIO_SDM
MSEL[2:0]
Fast mode - 001
Normal mode - 011
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