Power Sense Line; Power Optimization Techniques In The Intel Quartus Prime Software - Intel Agilex User Manual

5. Intel Agilex Power Optimization Techniques and Features
UG-20215 | 2019.04.02
Clock gating a large portion of your FPGA design could cause significant current
change over a short time period when the gated circuitry is enabled or disabled. The
maximum current step resulting from this clock gating should be sized such that it
does not create noise exceeding the maximum allowed AC noise specification, as
determined by the PDN decoupling design on your PCB. You can control the current
step size by dividing a large gated area into smaller sub-regions and staging those
regions to enter or exit power gating sequentially.
For more details, refer to the Clock Gating section in the Intel Agilex Clocking and PLL
User Guide.
Related Information
Intel Agilex Clocking and PLL User Guide
Provides more information about clock gating.

5.4. Power Sense Line

Intel Agilex devices support the power sense line feature.
pins are differential remote sense pins used to monitor the V
You must connect the
the regulator supplying V
5.5. Power Optimization Techniques in the Intel Quartus Prime
Software
The Intel Quartus Prime software offers power-driven compilation to fully optimize
device power consumption.
Power-driven compilation focuses on reducing the design's total power consumption in
synthesis and place-and-route stages. For detailed information, refer to the Intel
Quartus Prime Pro Edition User Guide: Power Analysis and Optimization.
Related Information
Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization
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and
VCCLSENSE GNDSENSE
rail that supports the remote voltage sensing feature.
CCL
and
VCCLSENSE
power supply.
CC
pins to the remote sense inputs for
® ™
Intel Agilex Power Management User Guide
GNDSENSE
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