Pll Input Clock Switchover - Intel Agilex User Manual

2. Intel Agilex Clocking and PLL Architecture and Features
UG-20216 | 2019.04.02
Intel Agilex devices support the following PLL-to-PLL cascading modes for I/O bank I/O
PLL:
• I/O-PLL-to-I/O-PLL cascading via dedicated cascade path—upstream I/O PLL and
downstream I/O PLL must be in the same I/O column.
• I/O-PLL-to-I/O-PLL cascading via core clock fabric—no restriction on locations of
upstream and downstream I/O PLL.
The
permit_cal
output of the upstream I/O PLL in both PLL cascading modes.
The following figures show the connectivity required between the upstream and
downstream I/O PLL for both the PLL cascading modes.
Figure 16. I/O-PLL-to-I/O-PLL Cascading Via Dedicated Cascade Path
Figure 17. I/O-PLL-to-I/O-PLL Cascading Via Core Clock Fabric
Note:
(1) You may connect any of the outclk from the upstream I/O PLL to the refclk port in the downstream I/O PLL when cascading the I/O PLL via

2.2.11. PLL Input Clock Switchover

The clock switchover feature allows the I/O PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
where a system turns to the redundant clock if the previous clock stops running. The
design can perform clock switchover automatically when the clock is no longer
toggling or based on a user control signal,
Send Feedback
input of the downstream I/O PLL must be connected to the
UPSTREAM_IOPLL
refclk cascade_out
reset
outclk[8:0]
UPSTREAM_IOPLL
refclk
outclk[0] (1)
reset
core clock fabric.
adjpllin
locked
permit_cal
reset
locked permit_cal
refclk
reset
.
extswitch
Intel
locked
DOWNSTREAM_IOPLL
locked
outclk[8:0]
DOWNSTREAM_IOPLL
locked
outclk[8:0]
® ™
Agilex Clocking and PLL User Guide
19