Clocking Lvds Serdes Receivers; Lvds Serdes Receiver Modes - Intel Agilex User Manual

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
• If you bypass the deserializer in SDR mode:
— The IOE data width is 1 bit.
— Registered input path requires a clock.
— Data is passed directly through the IOE.
• If you bypass the deserializer in DDR mode:
— The IOE data width is 2 bits.
—
rx_inclock
rx_in
— You must control the data-to-clock skew.
You cannot use the DPA and data realignment circuit when you bypass the deserializer.

5.3.2. Clocking LVDS SERDES Receivers

The I/O PLL receives the external clock input and generates different phases of the
same clock. The DPA block automatically chooses one of the clocks from the I/O PLL
and aligns the incoming data on each channel.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that compensates for
any phase difference between the DPA clock and the data realignment block. If
necessary, the user-controlled data realignment circuitry inserts a single bit of latency
in the serial bit stream to align to the word boundary. The deserializer includes shift
registers and parallel load registers, and sends a maximum of 10 bits to the internal
logic.
The physical medium connecting the transmitter and receiver SERDES channels may
introduce skew between the serial data and the source-synchronous clock. The
instantaneous skew between each SERDES channel and the clock also varies with the
jitter on the data and clock signals as seen by the receiver. The three different modes
—non-DPA, DPA, and soft-CDR—provide different options to overcome skew between
the source synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the
serial data.
Non-DPA mode allows you to statically select the optimal phase between the source
synchronous clock and the received serial data to compensate skew. In DPA mode, the
DPA circuitry automatically chooses the best phase to compensate for the skew
between the source synchronous clock and the received serial data. Soft-CDR mode
provides opportunities for synchronous and asynchronous applications for chip-to-chip
and short reach board-to-board applications for SGMII protocols.
Note: Only the non-DPA mode requires manual skew adjustment.

5.3.3. LVDS SERDES Receiver Modes

The Intel Agilex devices support the following receiver modes:
• Non-DPA mode
• DPA mode
• Soft-CDR mode
Send Feedback
clocks the IOE register. The clock must be synchronous to
.
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Agilex General Purpose I/O and LVDS SERDES User Guide
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