3. Intel Agilex I/O Termination
UG-20214 | 2019.04.02
Figure 13.
Dynamic R
Transmitter
Rs
Receiver
50 Ω
3.2.2. OCT Calibration Block
You can calibrate the OCT using the OCT calibration block available in each I/O bank.
There is two OCT calibration block for each GPIO bank. Every OCT calibration block
can calibrate the I/O buffer located in the same row but not the I/O of different row.
Example, OCT calibration block in bank 2A can be used to calibrate I/O from bank 2A,
2B, 2C, and 2D but not the I/O from bank 3A, 3B, 3C, and 3D.
The OCT calibration process uses the
block in a given I/O bank for series- and parallel-calibrated termination:
•
Each OCT calibration block has an external 240 Ω reference resistor associated
with it through the
•
Connect the
•
The
RZQ
the pin is located.
•
The RZQ pin is a dual-purpose I/O pin and functions as a general purpose I/O pin
if you do not use the calibration circuit.
•
Only the 1.2 V
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OCT in Intel Agilex Devices
T
V CCIO
100 Ω
100 Ω
GND
FPGA OCT
V CCIO
2 x R
T
2 x R
T
GND
FPGA OCT
pin.
RZQ
pin to GND through an external 240 Ω resistor.
RZQ
pin shares the same
VCCIO_PIO
bank can use the OCT calibration block.
VCCIO_PIO
V CCIO
2 x R
Z 0 = 50 Ω
2 x R
GND
V CCIO
100 Ω
Z 0 = 50 Ω
100 Ω
GND
pin that is available in every calibration
RZQ
supply voltage with the I/O bank where
®
™
Intel
Agilex
General Purpose I/O and LVDS SERDES User Guide
Receiver
T
T
50 Ω
FPGA OCT
Transmitter
Rs
FPGA OCT
25