Output Register Bank For Fixed-Point Arithmetic; Floating-Point Arithmetic; Input Register Bank For Floating-Point Arithmetic - Intel Agilex User Manual

If the double accumulation register is enabled, an extra clock cycle delay is added into
the feedback path of the accumulator.
This register has the same settings as the output register bank.
By enabling this register, you can have two accumulator channels using the same
number of variable precision DSP block. This is useful when processing interleaved
complex data (I, Q).

2.1.10. Output Register Bank for Fixed-Point Arithmetic

The positive edge of the clock signal triggers the 74-bit bypassable output register
bank and is cleared after power up.
The following variable precision DSP block signals control the output register per
variable precision DSP block:
•
CLK
•
ENA[2..0]
•
CLR[1]
Related Information
Configurations for Input, Pipeline, and Output Registers
Provides information about restrictions on fixed-point arithmetic output registers.

2.2. Floating-Point Arithmetic

2.2.1. Input Register Bank for Floating-Point Arithmetic

The input register banks for floating-point DSP blocks are available for the following
input signals:
•
fp32_adder_a
•
fp32_adder_b
•
fp32_mult_a
•
fp32_mult_b
•
fp16_mult_top_a
•
fp16_mult_top_b
•
fp16_mult_bot_a
•
fp16_mult_bot_b
• Dynamic ACCUMULATE control signal
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Intel Agilex Variable Precision DSP Blocks User Guide
20
2. Intel Agilex Variable Precision DSP Blocks Architecture
on page 62
UG-20213 | 2019.04.02
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