Maximum Allowable External As_Data Pin Skew Delay Guidelines - Intel Agilex Configuration User Manual

Figure 38. AS Configuration Serial Input Timing Diagram
Note: For more information about the timing parameters, refer to the Intel Agilex Device Datasheet.

3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines

You must minimize the skew on the AS data pins.
Skew delay includes the following elements:
• The delay due to the differences in board traces lengths on the PCB
• The capacitance loading of the flash device
The table below lists the maximum allowable skew delay depending on the AS_CLK frequency. Intel recommends that you to
perform IBIS simulations to ensure that the skew delay does not exceed the maximum delay specified in this table.
Table 27. Maximum Skew for AS Data Pins in Nanoseconds (ns)
Symbol
T Skew delay for
ext_skew
Intel ® Agilex ™ Configuration User Guide
94
nCSO
AS_CLK
T
ext_delay
AS_DATA IN0
Description
for the frequency specified
AS_DATA AS_CLK
IN1 INn
Frequency
133 MHz
125 MHz
115 MHz
108 MHz
100 MHz
<100 MHz
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.10.09
Min Typical Max
— — 3.60
— — 4.00
— — 4.20
— — 4.60
— — 5.0
— — 5.0
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