Reset Release Intel Fpga Ip - Intel Agilex Configuration User Manual

2. Intel Agilex Configuration Details
UG-20205 | 2019.10.09

2.3. Reset Release Intel FPGA IP

Intel requires that you either use the Reset Release Intel FPGA IP or the
hold your design in reset until configuration is complete.
The Reset Release Intel FPGA IP is available in the Intel Quartus Prime Software. This IP consists of a single output signal,
. The
nINIT_DONE
and HPS First configuration modes. Intel recommends that you hold your design in reset while the
or while the
INIT_DONE
When you instantiate the Reset Release IP in your design, the SDM drives the
not consume any FPGA fabric resources, but does require routing resources.
Figure 6. Reset Release Intel FPGA IP nINIT_DONE Internal Connection
Send Feedback
signal is the core version of the
nINIT_DONE
pin is low.
Reset Release IP
INIT_DONE
pin and has the same function in both FPGA First
INIT_DONE
nINIT_DONE
Board
Intel FPGA
nINIT_DONE
Reset
Application Logic
signal routed back in through a pin to
signal is high
nINIT_DONE
signal. Consequently, the IP does
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