Intel ® Agilex ™ General Purpose I/O And Lvds Serdes Overview; Intel Agilex I/O And Differential I/O Buffers - Intel Agilex User Manual

UG-20214 | 2019.04.02
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1. Intel Agilex
Overview
The Intel
Secure Device Manager (SDM) I/O interface and a Hard Processor System (HPS) I/O
interface. Each I/O interface is designed to meet different interfacing requirements.
The General Purpose I/O interface system can support:
• 1.2 V single-ended non-voltage referenced Joint Electron Device Engineering
Council (JEDEC) compliant I/O standards.
• 1.2 V single-ended and differential voltage referenced JEDEC compliant I/O
standards.
• 1.5 V true differential I/O compatible with LVDS, RSDS, Mini-LVDS, and LVPECL
I/O standards.
• DDR4 memory interface up to 1600 MHz with a Hard Memory Controller (HMC).
• LVDS serializer/deserializer (SERDES) interface up to 1.6 Gbps.
The SDM and HPS I/O interfaces can support 1.8 V single-ended non-voltage
referenced I/O standard for SDM and HPS interfacing.
Related Information
Intel Agilex Data Sheet

1.1. Intel Agilex I/O and Differential I/O Buffers

The I/O bank within the GPIO interface supports differential and single-ended I/O
standards. The GPIO bank has true differential I/O buffers using the 1.5 V True
Differential Signaling I/O standard, which is compatible with the LVDS, RSDS, Mini-
LVDS, and LVPECL I/O standards. The true differential buffer forms a pair of
unidirectional true differential channels. Half of the true differential channels support
dedicated transmitter pins and the other half support dedicated true receiver pins.
Refer to the device pin-out files for locations of dedicated receiver and transmitter
channels.
Differential voltage referenced output pins are not true differential output pins. The
differential voltage referenced I/O standards use two single-ended output pins where
one of the output pins is inverted.
The I/O bank within the HPS and SDM interfaces supports single-ended IO standard.
Different power supplies power the Intel Agilex I/O buffer:
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
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accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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™
General Purpose I/O and LVDS SERDES
® ™
Agilex I/O system includes a general purpose I/O (GPIO) interface, a
ISO
9001:2015
Registered