Guideline: Configuration Constraints - Intel Agilex User Manual

3.4. Guideline: Configuration Constraints

The I/O PLL configuration must obey the following constraints:
• The phase frequency detector (PFD) and VCO each have a legal frequency range
of operation.
•
The loop filter settings must be appropriate for the
selected bandwidth mode.
If any of these configuration constraints are violated, the I/O PLL may fail to lock or
may exhibit poor jitter performance.
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Intel Agilex Clocking and PLL User Guide
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3. Intel Agilex Clocking and PLL Design Considerations
counter value and user-
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UG-20216 | 2019.04.02
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