Dsp And M20K Power Gating; Clock Gating - Intel Agilex User Manual

Parameters
Direct format coefficient m
Direct format coefficient b
Direct format coefficient R
(5)
Linear format N
Translated voltage value unit
(5)
Enable PAGE command

5.2. DSP and M20K Power Gating

Power gating of the DSP blocks and M20K memory blocks is enabled via the
configuration RAM (CRAM) bits.
Intel Agilex devices support power gating for both DSP blocks and M20K memory
blocks. By default, the Intel Quartus Prime software automatically configures unused
DSP blocks and M20K memory blocks to be power gated.

5.3. Clock Gating

Clock gating can be used to reduce dynamic power consumption. When an application
is idle, its clock can be gated temporarily and ungated based on wake-up events. This
is done using user logic to enable or disable the programmable clock routing.
You can perform dynamic power reduction by gating the clock signals of any circuitry
not used by the design in the Intel Agilex devices. The sector clock gating is done at
the multiplexer level.
(7)
N is the exponent of a 5-bit two's compliment integer.
® ™
Intel Agilex Power Management User Guide
26
(5)
Signed integer: -32768 to 32767
(5)
Signed integer: -32768 to 32767
(5)
Signed integer: -128 to 127
Signed integer: –16 to 15
(5)
5. Intel Agilex Power Optimization Techniques and Features
Value
If the voltage output format is the Auto
discovery or Direct format, you must
set the following parameters:
•
•
•
If the voltage regulator is the Linear
format, you must set the Linear format
N parameter.
Direct format coefficient m of the slave
device type when the operation mode
is PMBus Master.
Direct format coefficient b of the slave
device type when the operation mode
is PMBus Master.
Direct format coefficient R of the slave
device type when the operation mode
is PMBus Master.
Output voltage command when the
voltage output format is set to the
Linear format.
millivolts Indicates the translated output voltage
is in millivolts (mV) or volts (V).
volts
Enable By enabling the PAGE command, the
FPGA PMBus Master mode will use the
Disable
PAGE command to set all the output
channels on registered regulator
modules to respond to
VOUT_COMMAND
UG-20215 | 2019.04.02
Description
Direct format coefficient m
Direct format coefficient b
Direct format coefficient R
(7)
.
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