Fp16 Half-Precision Floating-Point Arithmetic Functions - Intel Agilex User Manual

Figure 32. FP32 Vector Two Mode
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
fp32_mult_a[31:0]
fp32_mult_b[31:0]

3.2.2. FP16 Half-Precision Floating-Point Arithmetic Functions

The FP16 half-precision floating-point arithmetic DSP can perform the following:
• Sum of two multiplication
• Sum of two multiplication with addition
• Sum of two multiplication with accumulation
• Vector one
• Vector two
• Vector three
Each of the functions supports:
• Extended precision format
• Flushed precision format
• Bfloat16 and bfloat+ formats
3.2.2.1. FP16 Supported Precision Formats
The FP16 half-precision floating-point arithmetic functions support the following
formats:
• Flushed - use IEEE-754 half-precision format (binary16) for multiplier inputs and
FP16 multiplication/addition/subtraction operations.
• Extended - use IEEE-754 half-precision format (binary16) for multiplier inputs.
Use extended format for FP16 multiplication/addition/subtraction operations.
• Bfloat16 - multiplier inputs can be configured to accept 16-bit bfloat16 format or
19-bit extended bfloat16+ format. Use extended format for FP16 multiplication/
addition/subtraction operations.
The following table shows the differences between the formats:
® ™
Intel Agilex Variable Precision DSP Blocks User Guide
44
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
Input
Register
Bank
*Pipeline *Pipeline
Register Register
Bank Bank
Multiplier
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
*Pipeline *Pipeline
Register Register
*Pipeline
Bank Bank
Adder
Register
Bank
fp32_chainout[31:0]
UG-20213 | 2019.04.02
Output
Register fp32_result[31:0]
Bank
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
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