Jtag Configuration - Intel Agilex Configuration User Manual

3.4. JTAG Configuration

JTAG-chain device programming is ideal during development. JTAG-chain device configuration uses the JTAG pins to configure
the Intel Agilex FPGA directly with the
require you to program an external flash memory. You can also use JTAG to reprogram if image stored in memory is corrupt,
preventing the device from configuring using the AS scheme.
The Intel Quartus Prime software generates a
JTAG programmer to configure the Intel Agilex device. The Intel FPGA Download Cable II and the Intel FPGA Ethernet Cable
both can support the V
Code File (
.jbc
Intel Agilex devices automatically compress the configuration bitstream. You cannot disable compression in Intel Agilex
devices.
Table 22. Intel Agilex Configuration Data Width, Clock Rates, and Data Rates
Mode
Passive JTAG
Related Information
Programming Support for Jam STAPL Language
Intel ® Agilex ™ Configuration User Guide
70
file. Configuration using the JTAG device chain is faster because it does not
.sof
.sof
supply at 1.8 V. Alternatively, you can use the Jam*STAPL Format File (
CCIO_SDM
) for JTAG configuration.
Data Width (bits)
1
containing the FPGA design information. You can use the
Max Clock Rate
30 MHz
3. Intel Agilex Configuration Schemes
UG-20205 | 2019.04.03
with a
.sof
) or Jam Byte
.jam
Max Data Rate MSEL[2:0]
30 Mbps 3'b111
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