Intel Agilex Clocking And Pll Architecture And Features; Clock Networks Architecture And Features; Clock Network Architecture - Intel Agilex User Manual

UG-20216 | 2019.04.02
Send Feedback

2. Intel Agilex Clocking and PLL Architecture and Features

2.1. Clock Networks Architecture and Features

2.1.1. Clock Network Architecture

Each Intel Agilex device is divided into a number of evenly sized clock sectors.
Figure 1. Clock Sector Floorplan for Intel Agilex Devices
This figure shows an example of the clock sectors in an Intel Agilex device, which is implemented as an array
of sectors—5 rows and 6 columns in this example. I/O banks are at the top and bottom of the Intel Agilex
device.
2.1.1.1. Clock Network Hierarchy
The Intel Agilex clock network is organized in a hierarchy with 3 levels.
Figure 2. Clock Network Hierarchy
Clock Source
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
First Level Second Level
Programmable
Clock Routing 32
SCLK
I/O Bank Row
Clock Sector
I/O Bank Row
Third Level
32 6
Row Clock
ISO
9001:2015
Registered