Analog Devices ADRV9005 Reference Manual page 94

Reference Manual
MICROPROCESSOR AND SYSTEM CONTROL
For a specific channel, Power Savings Mode 1 or higher is disallowed when the enableRiseToAnalogOnDelay is less than t
►
API Programming and Default Values for Timing Parameters
There is a set of API commands to configure the timing parameters. Because the timing parameters are related to the channel power saving
mode, set the channel power saving mode first before configuring the timing parameters. The API command adi_adrv9001_powerSavingAnd-
MonitorMode_ChannelPowerSaving_Configure( ) sets the channel power saving mode for a specified channel when the channel is in the
standby or calibrated state. After that, use the API command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) to configure the
timing parameters for the selected channel. The following data structure holds all the ADRV9001 required timing parameters:
typedef struct adi_adrv9001_ChannelEnablementDelays
{
uint32_t riseToOnDelay;
powered up */
uint32_t riseToAnalogOnDelay;
commences */
uint32_t fallToOffDelay;
powered down */
uint32_t guardDelay;
uint32_t holdDelay;
} adi_adrv9001_ChannelEnablementDelays_t
Note that the ADRV9001 reserves guardDelay for future use and forces it to 0 for both transmit and receive channels. In addition, for the
transmit channel, reserve holdDelay for future use and force it to 0. For the receive channel, reserve fallToOffDelay for future use and force it
to 0. Call the API command adi_adrv9001_Radio_ChannelEnablementDelays_Configure( ) when the channel is in the standby or calibrated
state.
To set all those timing parameters properly, gather prior knowledge about the ADRV9001 timing parameters (ADRV9001 provides to the user)
as well as helping parameters such as the transmit and receive propagation delay. The prior timing parameters include enableSetupDelay,
propagationDelay, and maximum intended power savings mode, t
Table 36 summarizes all these timing parameters for both transmit and receive. Note that all timing parameters specified in units of time
assume a system clock frequency of 184.32 MHz. If using a different system clock frequency, adjust it by:
scaleFactor = 184.32 (MHz)/system clock Frequency
Table 36. Prior Tx/Rx Timing Parameters
No PLL Retuning at Frame Boundary (Use Case in
enableSetupDelay Analog Power-Up*scaleFactor
propagationDelay From user's own measurement
t PLL Tuning + PLL Power-Up *scaleFactor
PowerUpPSM1
t PLL Tuning + LDO Tuning + PLL Power-Up *scaleFactor
PowerUpPSM2
The system clock frequency depends on the profile, and the corresponding value is found under the TDD Enablement Delays tab in TES.
In addition, TES also displays the timing parameters provided by the ADRV9001 to determine the prior transmit/receive timing parameters, as
described in Figure 79, which shows the picture of TES where those timing parameters and the system clock for the user-selected profile are
located.
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/* Delay from rising edge until antenna switch (Tx) or LNA (Rx) is
/* Delay from rising edge until Tx/Rx analog power up procedure
/* Delay from falling edge until antenna switch (Tx) or LNA (Rx) is
/* Reserved for future use*/
/* Delay from falling edge until the Tx/Rx interface is disabled */
PowerUpPSM1
Figure
, and t .
PowerUpPSM2
77) PLL Retuning at Frame Boundary (Use Case in
PLL Tuning + Analog Power-Up *scaleFactor
Same as No PLL tuning case
PLL Power-Up *scaleFactor
LDO Tuning + PLL Power-Up *scaleFactor
ADRV9001
.
PowerUpPSM1
Figure 78)
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