Analog Devices ADRV9005 Reference Manual page 129

Reference Manual
FREQUENCY HOPPING
Figure 119 shows the relationship between Hop 1 and Hop 2 signals in a dual-hop mode of operation. Hop 1 and Hop 2 are triggered
independently but must not be triggered at the same time. There must be a minimum of 12 µs offset between Hop 1 and Hop 2 edges. The
timing of the channel setup signals is the same as the 'PLL Retune Mode'.
PLL Retune
In the PLL Retune mode, the time to the start of the Rx/Tx analog front end being powered up is the maximum of: t
and t , where t
chRiseToAnaOn FHProcessing
variable per profile between ~150 MHz and ~200 MHz. Retrieve the system clock for a desired profile from the 'TDD Enablement Delay' tab
in TES. t could be measured for a particular system clock by comparing the transition times between two profiles and subtracting
FHProcessing
the PLL retune time using the measurement described in the
t = 26.7 µs, and when system clock = 192 MHz, t
FHProcessing
Table 54. PLL Retune Time (PLL Calibration Mode = Fast)
Device Clock (MHz)
30 92.6
38.4 73.2
50 56.7
100 34.6
150 26
200 21.3
245.76 18.7
300 16.1
Table 55. PLL Retune Time (PLL Calibration Mode = Normal)
Device Clock (MHz)
30 380.3
38.4 347.4
50 327.7
100 291.2
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Figure 119. Dual-Hop Timing
= 20 µs. t = 20 µs in standard profile for 184.32 MHz system clock. The system clock is
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PLL Retune Measurement
FHProcessing
Figure 120. PLL Retune
PLL Loop BW = 1200 kHz
Average (µs)
6.1
5.8
5.3
3.3
3
2.4
1.2
1.1
PLL Loop BW = 1200 kHz
Average (µs)
41.5
36.7
45.1
51.7
section. For example when system clock = 152 MHz,
= 19.3 µs.
Std. (µs) Average (µs)
101.3
83.5
68.4
36.3
36.3
31.5
27
25.5
Std. (µs) Average (µs)
382.4
354
325.5
298
ADRV9001
+ t
pllRetune FHProcessing
PLL Loop BW = 300 kHz
Std. (µs)
4.3
4.4
5
2.6
2.6
2.2
3
2.1
PLL Loop BW = 300 kHz
Std. (µs)
51.5
21
30.4
38.6
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