Analog Devices ADRV9005 Reference Manual page 220

Reference Manual
POWER SAVING AND MONITOR MODE
There are two power-saving choices that can be applied for various TDD interframe scenarios: channel power saving (CPS) and system power
saving (SPS). Configure either or both options according to the system specifications.
Channel Power Saving (CPS)
Channel power saving saves power-on channel granularity for dynamic TDD interframe operations. Two kinds of power-saving events are
triggered by either transmitter/receiver enable pins or DGPIO pins, respectively. The configuration selects power-saving modes for both kinds of
events. Only power-down modes 0 to 2 can be configured for CPS.
TX_ENABLE/RX_ENABLE Pin Triggers Power Saving
The power saving triggered by the TX_ENABLE/RX_ENABLE pin powers up/down based on the TX_ENABLE/RX_ENABLE rising or falling
edges. The TX_ENABLE/RX_ENABLE rising edge powers up the components based on the power-down mode, and the falling edge powers
down them.
Figure 193 shows the TX/RX Enable pin powers up/down channels. If the transmitter/receiver enable pin power-down mode is set to mode 1,
the TX1/RX1 enable falling edge powers down the TX1/RX1 PLL and TX1/RX1 datapath, and the rising edge powers them up. The higher the
power-down mode, the longer the recovery time. Ensure the system has enough transition time between the power-down and power-up of the
same component if a high power-down mode is set. For example, if TX1 and RX1 use the same internal PLL and there is very short transition
time between the transmitter enable falling edge, and receiver enable rising edge, ensure mode 1 and 2 are not selected because the same
PLL and LDOs are always used.
DGPIO Triggers Power Saving
DGPIO pin-triggered channel power saving provides additional power saving than the TX/RX enable pin when it is enabled. Therefore,
if enabled, ensure the power-down mode triggered by DGPIO is larger than the TX/RX enable pin-triggered power-down mode. Both the
transmitter and receiver channels can be powered down at the DGPIO rising edge and powered up at the DGPIO falling edge. This is because
only one DGPIO is assigned for the transmitter and receiver channels. The DGPIO can only be allowed to pull up when both the TX enable and
RX enable are low.
Figure 194 shows an example when both the TX/RX enable and DGPIO pin trigger power saving is enabled. The grey time slots are the ones
when the transmitter/receiver must be active. If the transmitter and receiver transition time is not long enough to allow power-down mode 1 or
2, select the TX/RX enable pin power-down mode 0. However, DGPIO power saving can be engaged during time slots 2 and 3 by selecting
power-down mode 2 to power down both the transmitter/receiver LDOs and PLLs in slot 2 and slot 3 areas in which the transmitter and receiver
are inactive.
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Figure 193. TX/RX Enable Pin Triggers Power Saving
Figure 194. TX/RX Pin Triggers Power Saving and DGPIO Triggers Power-Down Saving
ADRV9001
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