Analog Devices ADRV9005 Reference Manual page 70

Reference Manual
DATA INTERFACE
Figure 42. Receive CSSI Timing with 8 Times Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles
Figure 43, Figure 44, and Figure 45
four, and eight times clock rates. The strobe pulse validates the start of the 16-bit data symbol, and the remaining data bits are ignored.
Figure 43. Receive CSSI Timing with 2 Times Data Clock Rate for 16-Bit Data Symbol (MSB First)
Figure 44. CSSI Receive Timing with 4 Times Data Clock Rate for 16-Bit Data Symbol (MSB First)
Figure 45. Receive CSSI Timing with 8 Times Data Clock Rate for 16-Bit Data Symbol (MSB First)
Four-Lane Mode CSSI
The four-lane mode receives the CSSI of each channel (Rx1 and Rx2). These are a 6-wire digital interface consisting of:
RX_DCLK_OUT: output clock synchronous data and strobe output signals.
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RX_STROBE_OUT: output signal indicating the first bit of the serial data sample.
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RX_IDATA0_OUT: output serial data stream of I sample low byte.
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RX_IDATA1_OUT: output serial data stream of I sample high byte.
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RX_QDATA2_OUT: output serial data stream of Q sample low byte.
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analog.com
show the receive CSSI (Rx1 and Rx2) in the frequency deviation mode with 16-bit data symbol with two,
ADRV9001
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