Receiver Datapath - Analog Devices ADRV9005 Reference Manual

Reference Manual
RECEIVER GAIN CONTROL
The process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding amount of digital gain before the
digital signal is sent to the user.
High Threshold
Triggers the gain attack event. Some detectors can have multiple high thresholds.
Low Threshold
Triggers the gain recovery event. Some detectors can have multiple low thresholds.
Threshold Overload
When a threshold is exceeded in a signal detector, it is an overload.
Threshold Underload
When a threshold is not exceeded in a signal detector, it is an underload.
Overrange Condition
An overrange condition is when the AGC is required to reduce the gain. This can either be a peak condition, where a programmable number of
individual overloads of a high threshold occurred within a defined period of time, or a power condition, where the measured power exceeds a
high power threshold.
Underrange Condition
An underrange condition is when the AGC is required to increase the gain. This can either be a peak condition, where a lower threshold is not
exceeded a programmable number of times within a defined period of time, or a power condition, where the measured power does not exceed
a low power threshold.

RECEIVER DATAPATH

Figure 162 shows the simplified receiver datapath and gain control blocks. The receivers have front-end attenuators before the mixer stage,
which are used to attenuate the signal in the analog domain to ensure the signal does not overload the receiver chain. Note: The ADRV9001
provides about 20dB gain so the front end gain attenuator further attenuates the signal from that level. There is also digital gain control
capability in the digital domain.
The figure shows that the receiver chain has a number of observation elements that monitor the incoming signal. These are used in either
the MGC or AGC mode. Firstly, there is an analog peak detector (APD) before the ADC. Being in the analog baseband, these peak detectors
see the signals first, and also see the interfering signals that overload the ADC but are filtered as they progress through the digital chain. The
second peak detector is called the HB peak detector because it monitors the data at the output of the half band (HB) filtering block in the
receiver chain.
There is also a power measurement detection block at the same output of the HB filtering block, which takes the RMS power of the received
signal over a configurable period of time.
Besides the front end gain control, this device also controls an external gain element through the analog GPIO (AGPIO) pins. In the digital
domain, this device further controls the digital gain in both the wideband (WB) and narrowband (NB) modes. To avoid saturating the output
signal due to the limitation of the bit-width of the data port, an optional interface gain (slicer) is applied at the end of the datapath by properly
shifting the data. The interface gain is automatically controlled internally inside the device by using the information provided from the receiver
signal strength indicator (RSSI) block or manually controlled through API commands.
Figure 162 shows that the gain control block has multiple inputs, which come from two peak detectors, and one power detector. By using the
information from those detectors, the gain control block controls the gain of the signal chain using a predefined gain table. Note that the default
gain table is loaded into the device during initialization. An API function adi_adrv9001_Rx_GainTable_Write() is called to load a custom gain
table or reconfigure the gain table. Note that this operation is done before performing initial calibrations.
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ADRV9001
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