Analog Devices ADRV9005 Reference Manual page 324

Reference Manual
POWER-SUPPLY RECOMMENDATIONS
Table 128. LDO Constraints
Index LDO
0 GP_LDO_1
1 DEV_CLK_LDO
2 CONVERTER_LDO
3 RX_1_LO_LDO
4 TX_1_LO_LDO
5 GP_LDO_2
6 RX_2_LO_LDO
7 TX_2_LO_LDO
8 CLK_PLL_SYNTH_LDO
9 CLK_PLL_VCO_LDO
10 CLK_PLL_LP_SYNTH_LDO
11 CLK_PLL_LP_VCO_LDO
12 LO1_PLL_SYNTH_LDO
13 LO1_PLL_VCO_LDO
14 LO2_PLL_SYNTH_LDO
15 LO2_PLL_VCO_LDO
16 AUX_PLL_SYNTH_LDO
17 AUX_PLL_VCO_LDO
18 SRAM_LDO
Set up the three different configurations, as shown in
Table 129. Power-Saving Configuration for Each LDO
Index LDO
0 GP_LDO_1
1 DEV_CLK_LDO
2 CONVERTER_LDO
3 RX_1_LO_LDO
4 TX_1_LO_LDO
5 GP_LDO_2
6 RX_2_LO_LDO
7 TX_2_LO_LDO
8 CLK_PLL_SYNTH_LDO
9 CLK_PLL_VCO_LDO
10 CLK_PLL_LP_SYNTH_LDO
11 CLK_PLL_LP_VCO_LDO
12 LO1_PLL_SYNTH_LDO
13 LO1_PLL_VCO_LDO
14 LO2_PLL_SYNTH_LDO
15 LO2_PLL_VCO_LDO
16 AUX_PLL_SYNTH_LDO
17 AUX_PLL_VCO_LDO
18 SRAM_LDO
Use the API function adi_adrv9001_powermanagement_Configure() to implement a device driver interface, allowing to set the ldoPowerSa-
vingsModes.
Configure the ldoPowerSavingModes struct in adi_adrv9001_PowerManagementSettings (GUI generated code sets all modes = 1) to
achieve the different power-saving configurations shown in
analog.com
Constraints
Do not power down or bypass.
Do not power down or bypass.
Power down only if all ADCs and DACs must be powered down.
Power down if RX1 is not needed.
Power down if TX1 is not needed.
Do not bypass.
Power down if RX2 is not needed.
Power down if TX2 is not needed.
Power down if the CLK_PLL_LP is in use.
Power down if the CLK_PLL_LP is in use.
Power down if the CLK_PLL is in use.
Power down if the CLK_PLL is in use.
Power down if LO1 is being externally supplied.
Power down if LO1 is being externally supplied.
Power down if LO2 is being externally supplied.
Power down if LO2 is being externally supplied.
Power down if the AUX_PLL is not required.
Power down if the AUX_PLL is not required.
Do not power down or bypass.
Figure 305, in this function by setting the LDO modes per
Configuration 2
1
1
5
5
5
1
5
5
1
1
1
1
1
2
2
2
1
1
1
Figure
Configuration 1
1
1
5
5
5
1
5
5
1
1
1
1
1
1
1
1
1
1
1
305.
ADRV9001
Input Pin Output Pin
VANA1_1P3 VANA1_1P0
VANA2_1P3 VANA2_1P0
VCONV_1P3 VCONV_1P0
VRX1LO_1P3 VRX1LO_1P0
VTX1LO_1P3 VTX1LO_1P0
VANA2_1P3 VANA2_1P0
VRX2LO_1P3 VRX2LO_1P0
VTX2LO_1P3 VTX2LO_1P0
VCLKSYN_1P3 N/A
VCLKVCO_1P3 VCLKVCO_1P0
VCLKSYN_1P3 N/A
VCLKVCO_1P3 VCLKVCO_1P0
VRFSYN1_1P3 N/A
VRFVCO1_1P3 VRFVCO1_1P0
VRFSYN2_1P3 N/A
VRFVCO2_1P3 VRFVCO2_1P0
VAXUSYN_1P3 N/A
VAUXVCO_1P3 VAUXVCO_1P0
VDIG_1P0 VDIG_0P9
Table 129 and Table 128 .
Configuration 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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