Api Programming - Analog Devices ADRV9005 Reference Manual

Reference Manual
DATA INTERFACE
Table 28. CMOS SSI Timing Specification (Continued)
CMOS SSI
CMOS Tx t Minimum
SETUP
CMOS Tx t Minimum
HOLD
Table 29. LVDS SSI Timing Specification
LVDS SSI
Rx t (Maximum)
DELAY
Tx t (Minimum)
SETUP
Tx t (Minimum)
HOLD

API PROGRAMMING

The ADRV9001 SSI configuration is performed in the chip initialization stage and based on the following data structure.
typedef struct adi_adrv9001_SsiConfig
{
adi_adrv9001_SsiType_e ssiType;
adi_adrv9001_SsiDataFormat_e ssiDataFormatSel;
adi_adrv9001_SsiNumLane_e numLaneSel;
adi_adrv9001_SsiStrobeType_e strobeType;
uint8_t lsbFirst;
uint8_t qFirst;
adi_adrv9001_SsiTxRefClockPin_e txRefClockPin;
bool lvdsIBitInversion;
bool lvdsQBitInversion;
bool lvdsStrobeBitInversion;
uint8_t lvdsUseLsbIn12bitMode;
bool lvdsRxClkInversionEn;
bool cmosDdrPosClkEn;
bool cmosClkInversionEn;
bool DdrEn;
bool rxMaskStrobeEn;
} adi_adrv9001_SsiConfig_t;
In the data structure, the previously mentioned SSI modes are defined for each Tx/Rx channel.
and some default values. Additionally, find the detailed data structure and enumerator description in the API Doxygen help file.
Table 30. SSI Configuration Parameters
Parameter
ssiType
ssiDataFormatSel
numLaneSel
strobeType
lsbFirst
qFirst
txRefClockPin
lvdsIBitInversion
lvdsQBitInversion
lvdsStrobeBitInversion
lvdsUseLsbIn12bitMode
analog.com
Timing
2 ns
2 ns
Timing
200 ps
220 ps
390 ps
Type Description
enum Set SSI type
enum Set SSI data format
enum Set SSI number of lanes
enum Set SSI strobe type
uint8_t Set LSB first
uint8_t Set Q data first
enum Set TX SSI reference clock output (TX_DCLK_OUT) options
bool Set LVDS SSI I bit differential pads polarity inversion
bool Set LVDS SSI Q bit inversion
bool Set LVDS SSI strobe bit inversion
uint8_t Set LVDS 12-bit mode
Description
Strobe/data setup to clock
Strobe/data hold after clock
Description
Clock to strobe/data delay
Strobe/data setup to clock
Strobe/data hold after clock
Table 30
ADRV9001
lists the SSI configuration parameters
Note
Default '0', MSB first
Default '0', I data first
Default 'false'
Default 'false,'' Rx SSI ignores
this field, I/Q lanes share the
configuration of "lvdsIBitInversion"
Default 'false''
Default '0', LVDS SSI uses 16-bit
mode
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