Analog Devices ADRV9005 Reference Manual page 103

Reference Manual
MULTICHIP SYNCHRONIZATION
An external clock module is required to generate the DEV_CLK and MCS pulses for multiple ADRV9001 devices. Each ADRV9001 receives a
DEV_CLK and an MCS signal. The MCS signals should arrive at all ADRV9001 devices within one DEV_CLK cycle as they must be sampled
by the DEV_CLK, as mentioned in
and each ADRV9001 device. Carefully tune the external clock module so that the pulses arrive at all ADRV9001 devices within one clock cycle
time.
The minimum MCS setup time requirement is 0.62 ns for the LVDS mode and 1 ns for the CMOS mode. The minimum hold time requirement
for the LVDS mode is 0 ns and 3 ns for the CMOS mode.
MCS Pulses
Figure 88 shows the MCS signal that must be received by the ADRV9001. There are six pulses. The first four pulses are for the analog
clock divider synchronization, and the last two are for the digital clock divider and SSI synchronization. Together, they synchronize all internal
components of the ADRV9001.
Pulse Width and Delay
Table 44 shows the minimum pulse width of each MCS pulse, as well as the wait time required after each pulse. Use this reference to design
MCS pulse generation.
Table 44. Minimum Time Requirement for MCS Pulse Width and Wait Time
Pulse No. Pulse Width (No. of Reference Clock Cycles)
1 ≥2
2 ≥2
3 ≥2
4 ≥2
5 ≥2
6 ≥2
MCS and Phase Synchronization
Enabling MCS guarantees the delay between the RF ports to the SSI (or reverse direction) to be deterministic, across all channels on one or
multiple ADRV9001 devices.
Additionally, the ADRV9001 also provides phase synchronization for the PLLs across multiple devices. Enable this option so that the data is
synchronized in time, and the phases of the PLLs are also synchronized.
Note: If choosing the MCSMODE_ENABLED mode, which does not guarantee phase synchronization, the process is done only once after the
device is initialized and at the calibrated state for the first time. This means after all MCS pulses are sent, and all ADRV9001 components are
synchronized, no more pulses are needed. The MCS is complete and no longer needs to run again unless the chip is reset.
If the MCSMODE_ENABLED_WITH_RFPLL_PHASE mode is selected MCS is done at the initialization stage like the MCSMODE_ENABLED
mode, and once complete, it guarantees phase synchronization and no longer requires MCS pulses. Whenever PLL changes, perform the
phase sync again to ensure the phase among all channels is synchronized, which is done automatically by the ADRV9001 device without any
user interaction.
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Figure 87. So, it is recommended that the layout has equal-length traces between the external clock module
Figure 88. MCS Pulses for Analog and Digital Synchronization
Wait Time After the Pulse Tn (µs)
>1
>1
>1
>100
>100
>1
ADRV9001
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