Analog Devices ADRV9005 Reference Manual page 203

Reference Manual
RECEIVER GAIN CONTROL
some extra fields, which are 1 bit of slicer gain or AGC gain change indicator and one of the following: zeros, interface gain, or AGC gain index.
For more details, see the Data Interface
Figure 176 is a block diagram of the digital gain control portion of the receiver chain, showing the locations of the various blocks in the simplified
datapath.
Figure 176 shows that digital gain control is performed in the WB/NB decimation block. In NB and WB applications, the digital gain control is
actually performed at different stages of the receiver data chain to achieve optimal performance, which is simplified in
must depend on the desired signal power alone and must be done only when all the interfering signals are filtered out, for example, close to the
end of the datapath. The slicer operation can either be controlled automatically by the device internally or externally through API commands.
When controlled internally, the RSSI block is used to determine the amount of interface gain. Note that there is also a fast attack algorithm for
automatic interface gain control algorithm. This is mainly to solve the signal saturation problem at the beginning when the Rx output signal level
is increased significantly in NB applications (such as in a TDD operation). As previously discussed, when the Rx output signal is very low, a
high interface gain is applied and when the Rx output signal level becomes very high, the interface gain must lower quickly to avoid saturation.
However, it takes some time to react to the signal level change in a normal operation mode. Therefore, the fast attack algorithm is designed
to solve this issue. Provide the maximum signal level target and the signal peak to average power ratio (PAPR) to help the automatic interface
gain control algorithm to produce the proper interface gain values.
The following sections describe four different digital gain control modes in the device.
Mode 1: No Digital Gain Compensation with Internal Interface Gain Control
In this mode, the digital gain block is used for gain correction. It applies a small amount of digital gain/attenuation to provide consistent gain
steps in a gain table. The premise is that because the analog attenuator does not have consistent steps in dB across its entire range, the digital
gain block is used to even out the steps for consistency (the default table uses the digital gain block to provide consistent 0.5 dB steps).
With internal control, the device automatically applies the interface gain determined by RSSI, which measures the input signal power right
before the slicer. Note that in the gain correction mode, interface gain less than 0 is not needed as the receiver output level should not exceed 0
dBFS through either AGC or MGC. When in NB applications, the interface gain range can be from 0 dB to 18 dB in 6 dB step size (0, 6, 12, and
18) to improve the sensitivity when a quantizer is used. In WB applications, as discussed earlier, the sensitivity is already satisfied by the high
sampling rate. So, the interface gain is always 0.
After applying the interface gain, the signal is provided to the data port. The baseband processor can retrieve the interface gain through API
commands to scale the power of the received signal to determine the power at the input to the device (or at the input to an external gain
element if included as a part of the digital gain compensation).
Mode 2: No Digital Gain Compensation with External Interface Gain Control
This mode is similar to mode 1, except the interface gain is controlled manually. Similarly, when in NB applications, the interface gain range is
selected from 0 dB to 18 dB in 6 dB step size when a quantizer is used, while in WB applications, the interface gain is fixed at 0 dB.
Mode 3: Digital Gain Compensation with Internal Interface Gain Control
The gain compensation is used in this mode, and the interface gain is determined internally. The device is loaded with the gain tables that
apply compensation for the analog front-end attenuation. Thus, as the analog front-end attenuation is increased, equal amount of digital gain is
analog.com
section.
Figure 176. Gain Control and Slicer Section of the Receiver Datapath
ADRV9001
Figure 176. The slicer
Rev. A | 203 of 377