Spi Test; Spi Main - Analog Devices ADRV9005 Reference Manual

Reference Manual
SERIAL-PERIPHERAL INTERFACE (SPI)
Table 21. SPI Bus Timing Constraint Values
Parameter Min
t 28 ns
CP
22 ns
t 10 ns
MP
t 3 ns
SC
t 0 ns
HC
t 2 ns
S
t 0 ns
H
t 3 ns
CO
3 ns
t t
HZM H
t 0 ns
HZS
Note: on the ADRV9001 (SPI sub device), SPI data in is read on the clock rising edge while SPI data out is written on the clock falling edge.
The SPI main device setup and hold times should account for this SPI data format.

SPI TEST

The ADRV9001 has a scratch SPI register 0x009 for the SPI read/write validation. The following procedures quickly check the SPI function
before the relative BBIC drivers are ready:
Power on the ADRV9001 properly.
►
Toggle the reset pin to reset the ADRV9001
►
Write register 0x0 with value 0x3C to set the ADRV9001 SPI to the 4-wire mode, or with value 0x24 to set the ADRV9001 SPI to the 3-wire
►
mode.
Write any value to scratch register 0x009, then read register 0x009 to validate if the read value is the same as the write value.
►
Use the oscilloscope to probe the SPI bus signal and check if the SPI controller follows the timing diagrams in
the above SPI validation cannot pass.
Also use the API adi_adrv9001_spi_Verify() to validate the SPI after the adi_adrv9001_spi_Configure() is set if the BBIC has the available
drivers.

SPI MAIN

The ADRV9001 contains an SPI) Main digital block, which can be utilized through the GPIO (either digital or analogue) pins to control external
components (for example, a PLL). This is separate from the SPI Sub functionality previously discussed.
the GPIO pin banks. The MCLK, MOSI, and MISO pins are currently fixed in assignment, and while the SPI Main functionality is enabled, these
pins cannot be assigned to any other functions.
Table 22. SPI Main Pin Mapping
Pin MCS0
GPIO0
✓
GPIO1
GPIO2
analog.com
Typical Max Description
SCLK period, 3-wire mode
SCLK period, 4-wire mode
SCLK pulse width
CSB setup time to first SCLK rising edge
Last SCLK falling edge to CSB hold
SDIO data input setup time to SCLK
SDIO data input hold time to SCLK
15 ns SCLK falling edge to output data delay (3-wire mode)
10 ns SCLK falling edge to output data delay (4-wire mode)
t (max) Bus turnaround time after baseband processor drives the last address bit
CO
t (max) Bus turnaround time after device drives the last data bit
CO
Figure 30. 3-Wire SPI Timing with Parameter Labels, SPI Read
1 1
MCS1 MCS2
✓
✓
1 1
MCS3 MCLK
ADRV9001
Figure 28 and Figure 29
Table 22 shows the SPI pin mapping on
2
MISO MOSI
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when