(Mcs) Input - Analog Devices ADRV9005 Reference Manual

Reference Manual
RF PORT INTERFACE INFORMATION
Table 119. DEV_CLK_IN Phase Noise Requirements for 1dB System PN Degradation Compared to an Ideal DEVICE CLOCK
Narrow PLL Loop Bandwidth (Approximately 50 kHz) (Default,
Typically <3 GHz)
Frequency Offset From
Carrier 122.88 MHz (dBc/Hz) 153.6 MHz (dBc/Hz) 245.76 MHz (dBc/Hz) 122.88 MHz (dBc/Hz)
100 Hz −113.02
1000 Hz −125.02
10 kHz −133.02
100 kHz −137.02
1 MHz −133.02
10 MHz −104.02
Table 120. DEV_CLK_IN Phase Noise Requirements for LMR Type Applications
Frequency Offset From Carrier
100 Hz
1000 Hz
10 kHz
100 kHz
10 MHz
CONNECTION FOR MULTICHIP SYNCHRONIZATION (MCS) INPUT
An LVDS type MCS signal applied between MCS + (D7) and MCS − (D8) pins is used to provide time alignment synchronization for both the RF
and datalink systems. Similar to the device clock input signal, use a clock source with fast rise and fall times as an MCS input signal. Implement
PCB traces for routing MCS signals by following the guidelines similar to the LVDS mode device clock input trace.
Note: The CMOS type of MCS signal applied only on the D7 pin is also supported.
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−111.08 −107.00
−123.08 −119.00
−131.08 −127.00
−135.08 −131.00
−131.08 −127.00
−102.08 −98.00
PLL Loop Bandwidth Optimized for LMR Type Applications, 38.4 MHz (dBc/Hz)
−106
−151
−151
−151
−151
Wide PLL Loop Bandwidth (Approximately 300 kHz) (User Configured,
Typically >3 GHz )
153.6 MHz (dBc/Hz)
−114.02 −112.08
−127.02 −125.08
−138.02 −136.08
−146.02 −144.08
−147.02 −145.08
−118.02 −116.08
ADRV9001
245.76 MHz (dBc/Hz)
−108.00
−121.00
−132.00
−140.00
−141.00
−112.00
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