Analog Devices ADRV9005 Reference Manual page 287

Reference Manual
RF PORT INTERFACE INFORMATION
Table 118. Device Clock Input Interface Modes Description (Continued)
Voltage Applied at MODEA Device Clock Input Electrical
Pin Interface
1.8 V CMOS or XTAL
By applying 1.8 V to the MODEA pin A for CMOS interface mode, apply a clipped sinewave clock signal from a TCXO to the pin DEV_CLK_IN+
(E7) through an AC-coupling capacitor, and leave the pin DEV_CLK_IN-(E8) unconnected, as shown in
Connect an Xtal to both DEV_CLK_IN+ and DEV_CLK_IN- pins with a DC voltage between 0.45 V and 1.8 V applied to the MODEA pin, as
shown in Figure 274.
When selecting the LVDS mode input clock interface with the MODEA pin grounded, use an external clock as the reference clock for the RFPLL
and the clocking PLL on the device, and thus it must be a very clean clock source. Connect the external clock inputs to the DEV_CLK_IN+
(E7) and DEV_CLK_IN- (E8) balls through AC-coupling capacitors and terminate with 100 Ω, as shown in
device to a 200 mV voltage level.
the DEV_CLK signal is between 10 MHz and 1000 MHz. Ensure that the external clock peak-to-peak amplitude does not exceed 800mV (note:
the positive and negative side of the differential input pins should not exceed 400mV peak-to-peak.). For best synthesizer performance, a high
slew-rate signal is best with fast rise and fall times.
Device Clock Interface Modes
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DEV_CLK_OUT Divider Value Applied to
DEV_CLK_IN Signal
/2
Figure 275 shows the input impedance plot over the operating frequency. The operational frequency range of
Figure 272. LVDS Interface Mode
Figure 273. CMOS Interface Mode
Figure 274. Crystal (XTAL) Interface Mode
ADRV9001
Note
/XTAL (20MHz to 80MHz) with Nominal Gm multi-
plier = x2
CMOS (10MHz to 80MHz)
/XTAL (20MHz to 80MHz) with Nominal Gm multi-
plier = x4
Figure 273.
Figure 272. Bias the inputs on the
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