Receiver Demodulator; Receiver Narrowband Demodulator Subsystem - Analog Devices ADRV9005 Reference Manual

Reference Manual ADRV9001

RECEIVER DEMODULATOR

RECEIVER NARROWBAND DEMODULATOR SUBSYSTEM

The ADRV9001 receiver narrowband demodulator subsystem, denoted by rxnbdem, is the digital baseband back-end partition of the
ADRV9001 receiver channel. Note that the narrowband is commonly used in wireless communication systems. If the channel spacing (also
known as channel bandwidth) is 1 MHz or less, it is known as a "narrowband system," otherwise it is called a "wideband system." Figure 183
shows the rxnbdem subsystem, incorporating signal buffering, carrier frequency offset correction, programmable channel filtering, frequency
discrimination, narrowband programmable pulse shaping, and resampling function. The input of rxnbdem, driven by the receiver decimation
filters, is the zero intermediate frequency (ZIF) digital baseband IQ signal. There is programmability to bypass each block in the rxnbdem
subsystem. The output of rxnbdem is directly sent to the receiver SSI. Depending on the programmed functionality, the output can be frequency
deviation (I)-only or IQ.
Figure 183. Functional Diagram of rxnbdem
Signal FIFO
The Signal FIFO buffers the input IQ data stream, and it is applicable only in the CMOS SSI operation mode. The Signal FIFO depth is 2048.
As a result, it can store more than 85 ms at the sampling rate of 24 kHz.
Figure 184. Functional Diagram of Signal FIFO
Disable or enable the Signal FIFO based on requirements. As the Signal FIFO is disabled, this block is bypassed and cannot be written or read.
As the Signal FIFO is enabled, the writing and reading control of the Signal FIFO can be manipulated separately. The FIFO reading clock is
configurable and can be 1×, 2×, 4×, or 8× of the FIFO writing clock. Only 1× and 2× are supported for wideband modes, and the reading clock
rate cannot be above 61.44 MHz.
In the Signal FIFO, as shown in Figure 184, there is an output mux, which has two inputs: "Bypass" is driven by the input IQ stream to the FIFO
and "FIFO," is driven by the output IQ stream from the FIFO. The mux inputs can be switched on demand to drive the following modules in
rxnbdem.
The following example explains how to use the Signal FIFO.
Keep the mux at "Bypass" during the signal capturing phase before the wireless data link is established. The "FIFO" writing control is enabled
and reading control is disabled. Through the receiver SSI port, the baseband integrated circuit (BBIC) can keep on detecting the received
signal. Meanwhile, the Signal FIFO keeps on buffering the IQ stream. The FIFO writing overflow may or may not happen. If this happens, the
FIFO always stores the latest 2048 IQ data.
As the BBIC detects the desired receiver frame from the input data stream and estimates the right starting point of the wanted receiver frame,
and further the synchronous parameters, the BBIC can switch the mux from "Bypass" to "FIFO," then enable the reading control of the FIFO, to
process the stored data stream and the following data stream seamlessly.
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