Analog Devices ADRV9005 Reference Manual page 303

Reference Manual
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
SSI Data Port Trace Routing Recommendations
The data port interface transfers I/Q data between the BBIC/FPGA and ADRV9001 transmitter and receiver datapaths. There are two possible
modes of operation for the SSI data port:
CMOS-SSI mode (single-ended), with clock rate for data transfer up to 80 MHz.
►
LVDS-SSI mode (differential), with clock rate for data transfer up to 500 MHz DDR (1000 MHz data rate).
►
Follow the correct layout practice while routing the SSI signals.
If selecting the CMOS-SSI mode, single-ended signal lines between the ADRV9001 and BBIC/FPGA must be as short as possible. Also reduce
the trace capacitance to minimize the current needed by the ADRV9001 to drive the line. Refer to the ADRV9001 data sheet for details on pin
drive capabilities.
If selecting the LVDS-SSI mode, route all the LVDS signals as 100 Ω differential pairs.
When routing the PCB layout for the LVDS-SSI data lines, the designer must route the signals using stripline or microstrip traces. There are
►
positives and negatives for each.
Stripline has less loss and emits less EMI than microstrip lines, but stripline traces require the use of vias that can add complexity to the task
►
of controlling the impedance by adding line inductance.
Microstrip is easier to implement if the component placement and density allow for routing on the top layer, simplifying the task of controlling the
impedance.
If using the top layer of the PCB is problematic or the advantages of stripline are desirable, then follow these recommendations:
Minimize the number of vias.
►
Use blind vias wherever possible to eliminate via stub effects, and use micro vias to minimize via inductance.
►
If using standard vias, use maximum via length to minimize the stub size. For example, on an eight-layer board, use Layer 7 for the stripline
►
pair.
For each via pair, place a pair of ground vias close to them to minimize the impedance discontinuity.
►
In the LVDS-SSI mode:
For transmitter data port inputs, implement 100 Ω termination inside the ADRV9001.
►
For receiver data port outputs, implement 100 Ω termination at the receiver end.
►
Evaluation Board FMC Connector Signals Mapping
The ADRV9001 evaluation board uses the FPGA mezzanine card (FMC) standard connector as an interface to carrier boards.
outlines signal mapping used on the FMC connector implemented on the ADRV9001 evaluation board. The second column refers to the FMC
standard pinout names. For more information, refer to the ADRV9001 EVB schematic.
analog.com
Figure 291. Transmitter Power Supply Using RF Chokes
ADRV9001
Table 122
Rev. A | 303 of 377