Analog Devices ADRV9005 Reference Manual page 59

Reference Manual
SERIAL-PERIPHERAL INTERFACE (SPI)
R/Wb - Bit 15 of the instruction word determines whether a read or write data transfer occurs after the instruction byte write. Logic high indicates
a read operation; logic zero indicates a write operation.
D14:D0 - Bits A<14:0> specify the starting byte address for the data transfer during Phase 2 of the I/O operation.
All byte addresses, both starting and internally generated addresses, are assumed to be valid, i.e., if an invalid address (undefined register) is
accessed, the IO operation continues as if the address space is valid. For write operations, the written bits are discarded, and read operations
result in logic zeros at the output.
Single-Byte Data Transfer
When enSpiStreaming = 0, choose a single-byte data transfer. In this mode, CSB goes active-low, the SCLK signal activates, and the address
is transferred from the baseband processor to the device.
In LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by the next 14 bits in order from the
next LSB to MSB. The next bit signifies whether the operation is read (set) or write (clear). If the operation is a write, the baseband processor
transmits the next 8 bits LSB to MSB. If the operation is a read, the device transmits the next 8 bits LSB to MSB. Once the final bit is
transferred, the data lines return to their idle state, and the CSB line is driven high to end the communication session.
In MSB mode, the first bit transmitted is the R/Wb bit that determines if the operation is a read (set) or write (clear). The MSB of the address is
the next bit transmitted from the baseband processor, followed by the remaining 14 bits in order from the next MSB to LSB. If the operation is a
write, the baseband processor transmits the next 8 bits MSB to LSB. If the operation is a read, the device transmits the next 8 bits MSB to LSB.
Once the final bit is transferred, the data lines return to their idle state, and the CSB line is driven high to end the communication session.
Multibyte Data Transfer
When enSpiStreaming = 1, a multibyte data transfer is allowed. In this mode, data transfers across the bus are possible as long as the CSB
pin is low. The autoIncAddrUp controls how the address changes for subsequent writes or reads. When autoIncAddrUp = 1, the address
increments from the starting address for each subsequent data transfer until CSB is driven high. If the last register address is reached, the
next address accessed is 0x000. When autoIncAddrUp = 0, the address decrements from the starting address for each subsequent data
transfer. If address 0x000 is reached, the next address accessed is the last register location defined in the register map. The register address
0x000 sets up the SPI as well as functionality to soft reset the device. Uncontrolled data written to the register address 0x000 can cause SPI
misconfigurations or can reset the device. It is strongly recommended to control any data transfer using the multiByte data feature so that 0x000
is only written once at start-up.
For multibyte data transfers in LSB mode, the LSB of the address is the first bit transmitted from the baseband processor, followed by the
next 14 bits in order from the next LSB to MSB. The next bit signifies whether the operation is read (set) or write (clear). If the operation is a
write, the baseband processor transmits the next 8 bits LSB to MSB. After the MSB is received, the address increments or decrements based
on the autoIncAddrUp parameter. The baseband processor then continues to transfer data in 8-bit words, LSB to MSB, until the operation is
terminated by CSB being driven high. If the operation is a read, the device transmits the next 8 bits LSB to MSB. It then changes the address
and continues to transfer data in 8-bit words, LSB to MSB, until the operation is terminated by CSB being driven high.
For multibyte data transfers in MSB mode, the same process is followed except the first bit transferred indicates whether the operation is read
(set) or write (clear). The starting address is then transmitted by the baseband processor, MSB to LSB, followed by the data transfer, MSB to
LSB. The autoIncAddrUp parameter still controls the address increment or decrement.
Using the multibyte data transfer mode provides limited benefit because most registers in the device are not consecutive. Users determine if
multibyte data transfer enhances device control in their end application compared to the single command format.
Example: LSB-First Multibyte Transfer, Autoincrementing Address
To complete a 4-byte write starting at register address 0x02A and ending with register 0x02D in LSB-first format, follow these instructions when
programming the controller:
Make sure that fourWireMode = 1 - the device is configured to work with the 4-wire interface.
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Make sure that MSBFirst = 0 - SPI operates in LSB first mode.
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Make sure that autoIncAddrUp = 1 - the address pointer automatically increments.
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Make sure that enSpiStreaming = 1 - a multibyte data transfer is allowed.
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