Analog Devices ADRV9005 Reference Manual page 86

Reference Manual
MICROPROCESSOR AND SYSTEM CONTROL
Internal Path Delay is the delay between the SSI port and RF port for either the transmitter or receiver signal chains. It does not include any
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external components, and the ADRV9001 internal calibration algorithm calibrates the internal path delay during the chip initialization stage.
As part of the design of a custom setup, use the Internal Path Delay as an approximation, and further measure the entire Propagation Delay
of the setup to ensure the accurate transmitter/receiver timing on air in TDD operations.
The following sections detail how each delay presents in the transmitter and receiver signal chains, respectively, as well as the design choices
to make around them in different use cases.
Transmit Timing Definition
Transmit timing parameters define the events in order from the start of transmission at the ADRV9001 data port to the end when the transmit
burst is sent through the antenna to the air.
Figure 68 shows that a transmit burst consists of a series of valid transmit data with the option to pad guard data at the beginning and end
of the valid data. Based on the configured timing parameters configured, decide if full or partial of the guard data must be transmitted to the
air, and ensure the guard data usage is compliant with the standard requirement. Control the transmit enable pin to signal the start and end
of a transmit burst at the data port. Based on the transmitter enable signal and a set of configured transmit timing parameters, the ADRV9001
further controls the transmitter interface, transmit internal analog components, as well as the antenna switch (if it is controlled by the ADRV9001
instead of the user) to make sure the transmit burst is on air at a deterministic time as desired.
Transmit timing parameters shown in
user parameter (user provides to the ADRV9001), and helper parameters (determined by the user, which are not needed to provide to the
ADRV9001 but can be used to derive other required timing parameters).
specified in Table 34 are suggestions for optimal operation. No hardware, or software restrictions prevent from setting out of bound values. The
following sections specify the maximum programmable parameter value.
Table 34. Transmit Timing Parameters Description
Transmit Timing Parameters
enableSetupDelay (t )
TxEnaSetup
propagationDelay (t )
TxPD
enableRiseToOnDelay (t )
TxEnaRise2On
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Figure 68. Transmitter Timing Parameters (t
Figure 68 can be categorized into three types: ADRV9001 parameter (ADRV9001 provides to the user),
Provided by Bounds
ADRV9001 Min: N/A Max: N/A
Parameter
Helper
Min: N/A
Parameter
Max: N/A
User Parameter Min: 0
Typical: t
TxPD
Max: t + t
TxGT TxPD
> t )
TxPD TxEnaSetup
Table 34 further explains all these timing parameters. All bounds
Comments
No PLL retuning at frame boundary: 8 μs (analog power-up time)
PLL tuning at frame boundary: 758 μs (analog power-up time + PLL tuning time)
(The PLL tuning time 750 μs refers to when the internal LO is used and it
represents the worst case. When external LO is used, calculate and use own PLL
tuning time.)
Measure this parameter. It is profile and board layout dependent. It does not have
to provide to the ADRV9001. Use it to derive other parameters required by the
ADRV9001.
At minimum bound: antenna switch occurs t
transmit enable rising edge.
ADRV9001
+ some margin after
TxEnaSetup
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