Analog Devices ADRV9005 Reference Manual page 128

Reference Manual ADRV9001
FREQUENCY HOPPING
Figure 117. Frequency Hopping Typical TRx Timing for PLL Mux Mode
For the TRx operation, because a hop edge can mark both the start and end of an receiver or transmitter frame, the ADRV9001 guarantees that
the receiver and transmitter front ends are not powered up at the same time.
To achieve this, the ADRV9001 enforces a minimum setting for "RxRiseToAnaOn", specified by "analogGuardTime", to ensure that the receiver
front end is powered up after the transmitter front end is powered down.
No minimum setting for "TxRiseToAnaOn" is required. This is because the receiver front end is always powered down before the transmitter
front end power up routine starts, and no extra delay is required.
Figure 118. Requirement of RxRiseToAnaOn When Switching from Tx to Rx Hopping Frame
Dual Hop Timing
As per Table 48, 'PLL Retune with dual hop and hop table real-time process' (dual-hop mode) is identical to 'PLL Retune with hop table
real-time process' (single-hop PLL retune mode) with the addition of a second independent hop channel.
The frame timing of dual-hop mode is identical to Figure 107 and the channel enablement timings are identical to the 'PLL Retune Mode'
timings given in the Frequency Hopping Timing section for each hop channel.
The hop channels in dual-hop mode can be considered fully independent of each other so each hop-channel can have different frame timings,
and use either Tx or Rx independent of each other. The two hop channels only have one dependency on each other which is that they can not
be enabled at the same time i.e. Hop 1 and Hop 2 can not be triggered in sync.
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