Analog Devices ADRV9005 Reference Manual page 93

Reference Manual
MICROPROCESSOR AND SYSTEM CONTROL
Figure 78. Channel Power-Up and Power-Down Sequence in Different Power Savings Modes (PLL Re-Tune at Frame Boundary Case)
In this case, in all power saving modes, the PLL tuning is performed during enableSetupDelay instead of enableRiseToAnalogOnDelay.
Therefore, enableSetupDelay is much longer as it must allow time to tune the PLL. This means that the additional power-up duration
t is much shorter, and thus higher power savings can be achieved while setting the enableRiseToAnalogOnDelay to a much smaller
PowerUpPSM
value.
All the previously-mentioned descriptions are for internal LO scenarios. If the ADRV9001 is configured with the external LO mode, take the
responsibility to configure or retune the external PLLs. The ADRV9001 channel power-up and power-down sequence in different power saving
modes are same as in Figure
Impact of Power Savings on Timing Parameter Selection
As explained in the previous section, certain power savings modes cannot be entered if the enableRiseToAnalogOnDelay for that channel is not
greater than the duration of the additional power-up procedures needed in that mode.
For the transmit channels, if the propagation delay is quite large, the enableRiseToAnalogOnDelay chosen is already larger than the longest
power-up procedure duration, i.e. , t
For the receive channels, or transmit channels with short propagation delays, choose the enableRiseToAnalogOnDelay larger than t
to enter Power Savings Mode 1 and larger than t
being used, must also increase as it must always be larger than enableRiseToAnalogOnDelay. However, none of the other timing parameters
are affected by the power savings mode.
At the end of the frame, the power-down procedures take some small but finite time. For the receiver channels with large propagation delay, this
has no impact because the digital datapath might be on for a long time after the analog has powered down.
For the transmit channels or receive channels with short propagation delays, the minimum period between the channel enables falling edge
and the next rising edge must be enableHoldDelay plus the additional time needed for the extra power down procedures (t
t ). This prevents PLL or LDO from beginning power up in the new frame even before it has finished powering down in the old one.
PowerUpPSM2
Hardware and Software Restrictions for Timing Parameters
As previously mentioned, the bounds provided for each of these timing parameters and the guard times between rising and falling edges of the
receiver and transmitter enable signals are only guidelines. There are almost no hardware or software restrictions preventing from setting these
parameters anyway, including harmful or useless ways. There are a few restrictions, however, which are outlined as follows:
All provided timing parameters must be within the range of 0 ms to 91 ms. These bounds are specified, assuming the delay generation
►
blocks run at 184.32 MHz (system clock). If operating at a different frequency, the maximum bound scales accordingly. For example, if using
a 160 MHz clock, the maximum delay is 91 ms/184.32 × 160 = 79 ms.
For all channels, the enableRiseToOnDelay must be greater than or equal to the enableRiseToAnalogOnDelay, provided the enableRise-
►
ToOnDelay parameter is being used, i.e., the ADRV9001 is controlling antenna switch and/or LNA power.
For the transmitter channels, the enableHoldDelay must be less than or equal to the enableFallToOffDelay.
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For the receiver channels, the enableFallToOffDelay must be less than or equal to the enableHoldDelay.
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For a specific channel, Power Savings Mode 2 or higher is disallowed when the enableRiseToAnalogOnDelay is less than t
►
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77. Make sure the external LOs are ready before the enableRiseToAnalogOnDelay ends.
. In this case, there is no impact on the selection of the timing parameters.
PowerUpPSM2
PowerUpPSM2
to enter Power Savings Mode 2 and higher. The enableRiseToOnDelay, if it is
ADRV9001
PowerUpPSM1
,
PowerUpPSM1
.
PowerUpPSM2
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