Power Saving And Monitor Mode; Power-Down Modes - Analog Devices ADRV9005 Reference Manual

Reference Manual

POWER SAVING AND MONITOR MODE

The ADRV9001 is a high-performance integrated transceiver with low power considerations. To accommodate different user cases, the
ADRV9001 provides flexibility for users can flexibly trade-off between power consumption and performance with some of the following static
configuration options:
Clock phase-locked loop (PLL) option of high performance and low power
►
Clock PLL power option of high, medium, and low
►
ADC option of high performance or low power
►
ADC clock rate option of high, medium, and low
►
RF PLL local oscillator generator (LOGEN) optimization option of best phase noise and best power consumption
►
RF PLL power option of high, medium, and low
►
ARM clock rate option divided by 1, 2, and 4
►
Choose and configure these static options in the chip initialization stage. These are not allowed to change dynamically, except the ADC option,
high-performance ADC, and low-power ADC can be dynamically switched after the chip is initialized. Refer to the related sections in this user
guide for the above-mentioned options.
For TDD applications, the ADRV9001 defines different power-saving modes to meet the power-saving requirement in various user cases. Some
standards like DMR require the radio to enter periodical sleep and carrier detection cycles to save power (monitor mode) when it is not in
use. The ADRV9001 has dedicated hardware to meet this monitor mode requirement, and the ADRV9001 software has additional static and
dynamic power saving schemes to extend the power saving feature to a broader market beyond DMR.
The ADRV9001 defines five extra power-down modes that provide low to high power saving but short to long recovery time, and the details are
introduced in the following section.
There are three power-saving schemes for different power-saving applications.
Temporarily powering up/down the unused Tx/Rx channel in the calibrated state.
►
Dynamic interframe power saving runs automatically during all regular TDD transmitter/receiver operations. Configure DGPIO pins to support
►
additional power savings. Set all configurations by API through fast messages on the fly. The power saving software smartly handles the
powering up/down hardware components based on the PLL mapping and selected power saving mode. There are two power-saving choices
in interframe operations:
Channel power saving. Powers down a channel (both transmitter and receiver) based on power-down mode 0 to 2.
►
System power saving. Powers down the whole chip by power-down mode 3 to 5
►
Monitor Mode. Allows the baseband processor to move into a sleep state after it configures and moves the ADRV9001 into the monitor
►
mode. The ADRV9001 software controls the dedicated hardware and timers for periodical sleeping and detecting. Only power-down modes 3
to 5 are allowed in the monitor mode.
Choose proper power-down modes and power-saving schemes according to their application scenarios. The following sections explain the
detailed power-saving schemes.

POWER-DOWN MODES

Power-down modes dynamically power down and power up different levels of the ADRV9001 components.
power-down modes from low power saving but short recover time to high power saving but long recover time. Each higher power-down mode
powers down additional components than the lower mode. Power-down mode 3 is the exception.
Table 93. Power-Down Modes and Related Power-Down Components
Components TX
RX
System
analog.com
Power-Down Modes
Analog and Digital datapath
TX Internal PLLs
TX LDOs
Analog and Digital datapath
RX Internal PLLs
RX LDOs
CLK PLL
Converter and CLK PLL LDOs
Table 93
0 (Default) 1 2
x x x
x x
x
x x x
x x
x
ADRV9001
describes five extra
3 4 5
x x x
x x x
x x
x x x
x x x
x x
x x x
x x
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