Analog Devices AD9361 Reference Manual
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Analog Devices AD9361 Reference Manual

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One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

GENERAL INFORMATION

Complete specifications for the
should be consulted in conjunction with this user guide when using the evaluation board.
Additional information about the
is provided as a convince and informational for those who want to understand the low level operation of the part, it is not recommended
to attempt to create your own software. Analog Devices provides complete drivers for the
operating systems (Linux). The
•
Linux
wiki page
•
No-OS
wiki page
Support for these drivers can be found at:
•
Linux
engineer zone page
•
No-OS
engineer zone page
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
AD9361
AD9361
part can be found in the
AD9361
registers can be found in the
AD9361
and
AD9364
share the same API. The
AD9361 Reference Manual
Reference Manual
AD9361
data sheet, which is available from Analog Devices, Inc., and
AD9361 Register Map Reference
AD9361
and
Rev. A
| Page 1 of 128
Manual. While the register map
AD9361
for both bare metal/No-OS and
AD9364
drivers can be found at:
UG-570

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Summary of Contents for Analog Devices AD9361

  • Page 1: General Information

    Manual. While the register map is provided as a convince and informational for those who want to understand the low level operation of the part, it is not recommended to attempt to create your own software. Analog Devices provides complete drivers for the AD9361 for both bare metal/No-OS and operating systems (Linux).

  • Page 2: Table Of Contents

    Overview ..................16 LMT Overload Detector ............36 RFPLL Introduction ..............16 ADC Overload Detector ............36 AD9361 PLL Architecture ............16 Low Power Threshold ..............36 Reference Block ................16 Average Signal Power ..............36 Main PLL Block ................17 Settling Times ................
  • Page 3 AD9361 Reference Manual UG-570 Slow Attack AGC Gain Update Time ........40 Factory Calibrations ............... 71 Overloads in Slow Attack AGC Mode ........41 Overview ..................71 Slow Attack AGC and Gain Tables ........... 41 Internal DCXO ................71 Hybrid AGC Mode ..............42 Tx RSSI (Tx Monitor) ..............

  • Page 4: Revision History

    UG-570 AD9361 Reference Manual 0x035 = 0x1D (Tx VCO Calibration States) ......80 Dual Port TDD Functional Timing (CMOS) ....... 101 0x035 = 0x1E (Gain Control, Temp Sense Valid, AuxADC Dual Port Full Duplex Mode (CMOS) ........103 Valid) .................... 81 Dual Port FDD Functional Timing (CMOS) .......

  • Page 5: Introduction

    Literally direct current. In this document, DC refers to output frequency of the oscillator is controlled by an input undesired received power in the center of the complex received voltage level. These VCOs are part of the PLLs on the AD9361. baseband spectrum. AD9361...

  • Page 6: Initialization And Calibration

    UG-570 AD9361 Reference Manual INITIALIZATION AND CALIBRATION OVERVIEW AD9361 powers up into a sleep state for minimal power consumption. Before the AD9361 is operational, its clocks must be enabled and initial calibrations completed. The purpose of this section is to describe in detail the operation of the different initialization calibrations.

  • Page 7: Initalization Calibrations

    AD9361. Table 2 shows the Others are dependent on the carrier frequency, temperature, or sequence of calibrations. When the calibration sequence state other parameters and need to run initially and when certain holds a value of 0x1, the calibrations are complete.

  • Page 8: Bbpll Vco Calibration

    UG-570 AD9361 Reference Manual BBPLL VCO CALIBRATION The VCO calibration is run during the ad9361_set_rx_lo_freq and ad9361_set_tx_lo_freq functions. First, set up any The BBPLL VCO calibration must be run during initialization synthesizer setup registers, then write the fractional frequency of the AD9361 device.

  • Page 9: Baseband Rx Analog Filter Calibration

    AD9361 Reference Manual UG-570 BASEBAND Rx ANALOG FILTER CALIBRATION The baseband Rx analog filter calibration tunes the cutoff The Rx baseband analog filter calibration runs during the frequency of the third-order Butterworth Rx anti-aliasing filter. ad9361_set_rx_rf_bandwidth function. Calibration completion The Rx filter is located just before the ADC in the Rx signal can be monitored on a control output pin or by reading the path and is normally calibrated to 1.4×...

  • Page 10: Baseband Tx Analog Filter Calibration

    UG-570 AD9361 Reference Manual BASEBAND Tx ANALOG FILTER CALIBRATION The Tx baseband analog filter calibration runs as part of the ad9361_set_tx_rf_bandwidth. Calibration completion can be The baseband Tx analog filter calibration tunes the cutoff monitored on a control out pin or by reading calibration frequency of the third-order Butterworth Tx anti-imaging filter.

  • Page 11: Baseband Tx Secondary Filter

    AD9361 Reference Manual UG-570 BASEBAND Tx SECONDARY FILTER baseband signal path does not change with different wireless standards or clock frequencies, it should not need to be run The baseband Tx secondary filter is a tunable single pole filter again. The baseband DC offset correction values are stored for after the baseband Tx analog filter.

  • Page 12: Rf Dc Offset Calibration

    UG-570 AD9361 Reference Manual RF DC OFFSET CALIBRATION that actually change the front end gain, the calibration time is reduced. If the LUT does not hold a DC correction value for the The RF DC offset calibration should be run once during...

  • Page 13: Rx Quadrature Tracking Calibration

    AD9361 Reference Manual UG-570 Rx QUADRATURE TRACKING CALIBRATION cycles used for maximum calibration time. CLKRF is the clock rate at the output of the Tx FIR filter (after Tx FIR The Rx quadrature tracking uses the Rx data to continuously interpolation).

  • Page 14: Reference Clock Requirements

    To use the DCXO, connect an external crystal (XO) between the the data converters, digital filters, and I/O port. These PLLs all XTALP and XTALN pins of the AD9361. Valid crystal resonant require a reference clock input, which can be provided by an frequencies range from 19 MHz to 50 MHz.

  • Page 15: Reference Clock Setup And Operation

    AD9361 Reference Manual UG-570 REFERENCE CLOCK SETUP AND OPERATION The level for the clock should be 1.3 V p-p maximum(lower If the DCXO is not used, an external reference clock needs to swings can be used but will limit performance). This signal can be ac-coupled to XTALN (Pin M12).

  • Page 16: Rf And Bbpll Synthesizer

    For RFPLL INTRODUCTION best RFPLL performance, Analog Devices recommends selecting a reference clock or crystal that will be able to scale as The fundamental frequency of the RFPLLs is from 6 GHz to close to 80 MHz as possible.

  • Page 17: Main Pll Block

    The independent Rx and Tx PLLs use fractional-N techniques Analog Devices supplied lookup table to configure the VCO for to achieve the channel synthesis. The entire PLL is integrated stable performance over temperature. The main PLL output is on-chip, including the VCO and the loop filter.

  • Page 18: Charge Pump Current

    VTune Out bit, 0x23B[6] (Rx) or 0x27B[6] (Tx). VCO configuration consists of writing a few static registers For normal operation, these bits should be cleared. from an Analog Devices provided lookup table and then enabling LOCK DETECTOR an automatic calibration procedure to configure the VCO tune A lock detector bit is provided to indicate that the correspond- voltage (Vtune) and ALC.

  • Page 19: Synthesizer Look Up Table

    UG-570 SYNTHESIZER LOOK UP TABLE EXTERNAL LO Analog Devices provides synthesizer LUTs to generate the static Unlike the internal synthesizers that always operate from 6 GHz register writes needed for the VCO and loop filter. There is a set to 12 GHz no matter the RF tune frequency, the frequency of tables for FDD operation and a set of tables for TDD applied when an External LO is used is 2×...

  • Page 20: Bbpll Vco

    UG-570 AD9361 Reference Manual block, which is identical to, but independent from the reference BBPLL VCO scaler blocks for the RFPLLs. The reference block is configured The BBPLL VCO is a multiband ring oscillator with Kv of to buffer, multiply, or divide the device reference frequency 550 MHz/V that requires a frequency calibration before before passing to the to the BBPLL phase detector.

  • Page 21: Bbpll Charge Pump

    AD9361 Reference Manual UG-570 BBPLL CHARGE PUMP The charge pump has programmable output current from VCO TUNE 25 µA to 1575 µA in 25 µA steps. In addition, a programmable bleed current is available. This is an NMOS current source programmable from 0 µA to 316 µA.

  • Page 22: Fast Lock Profiles

    UG-570 AD9361 Reference Manual FAST LOCK PROFILES OVERVIEW A profile can be recalled by either issuing a single SPI command that contains the desired profile number and transfer bit, or AD9361 includes a fast lock mode that makes it possible to...

  • Page 23: Configuring And Using A Fast Lock Profile

    AD9361 Reference Manual UG-570 CONFIGURING AND USING A FAST LOCK PROFILE The Fast Lock registers (Address 0x25C through Address 0x25F for Rx, Address 0x29C through Address 0x29F for Tx) allow access to the internal memory area. Refer to Table 11 for Rx and Table 12 for Tx fast lock register contents. The following procedure describes how to define a particular profile to the currently programmed synthesizer frequency: If using faster lock (wide BW), determine fast lock delay and N.

  • Page 24: Fast Lock Pin Select

    UG-570 AD9361 Reference Manual Table 12. Tx Fast Lock Internal Addressing Program Address[7:4] Assignment Program Address[3:0] Assignment (written to 0x25D) Location of Setup Words profile0 Synthesizer Integer Word[7:0] 0x271[D7:D0] profile1 Synthesizer Integer Word[10:8] 0x272[D2:D0] profile2 Synthesizer Fractional Word[7:0] 0x273[D7:D0] profile3...

  • Page 25: Enable State Machine Guide

    AD9361 Reference Manual UG-570 ENABLE STATE MACHINE GUIDE The gray states displayed in Figure 9 require no user control OVERVIEW and will fall through to the next state after a set time. The AD9361 transceiver includes an enable state machine TO_ALERT signal is a setting in the ENSM Config 1 register.

  • Page 26: Modes Of Operation

    ALERT or WAIT, clear the bit. To move from ALERT to internal to the AD9361) or a level to advance the current state Tx or FDD, set the Force Tx On bit. To move back to ALERT or of the ENSM to the next state.
  • Page 27 AD9361 Reference Manual UG-570 ENABLE/TXNRX Pin Control TXNRX is high. In FDD, the logic level of TXNRX is ignored. The ENSM will exit the Rx, Tx, or FDD states when the ENABLE/TXNRX Pin Control mode is enabled by default. The ENABLE pin is pulled back to a logic low.
  • Page 28 UG-570 AD9361 Reference Manual FB_CLK ENABLE TXNRX POWER UP VCO ENSM STATE[3:0] WAIT ALERT ALERT ALERT Figure 12. ENABLE Pulse Mode, FDD (Minimum Pulse Width = One FB_CLK Cycle) FB_CLK SPIWRITE ENABLE TXNRX POWER UP VCO ENSM STATE[3:0] WAIT ALERT...
  • Page 29 AD9361 Reference Manual UG-570 ENSM and RF VCO Calibrations In TDD, the synthesizers do not remain locked all the time. While in the Rx state, the Tx synthesizer is disabled to save The ENSM controls an internal signal that tells the Rx and Tx power.

  • Page 30: Sleep State

    AD9361 Reference Manual SLEEP STATE AD9361 is now in the SLEEP state. To wake up the AD9361, enable digital clocks and BBPLL, AD9361 initially powers up in a very low power state called and then move into the ALERT state.

  • Page 31: Filter Guide

    AD9361 Reference Manual UG-570 FILTER GUIDE OVERVIEW Tx FIR The first digital filter in the Tx signal path is a programmable This section contains a description of the analog and digital polyphase FIR filter. The Tx FIR filter can also interpolate by a filtering available in both the Tx and Rx signal paths of the factor of 1, 2, or 4, or it can be bypassed if not needed.

  • Page 32: Tx Analog Filter Blocks

    UG-570 AD9361 Reference Manual Tx HB3/INT3 Tx ANALOG FILTER BLOCKS Tx HB3/INT3 provides the choice between two different fixed- Analog filtering after the DAC reduces spurious outputs by coefficient interpolating filters. Tx HB3/INT3 can interpolate removing sampling artifacts and providing general low-pass by a factor of 2 or 3, or it may be bypassed.

  • Page 33: Rx Signal Path

    AD9361 Reference Manual UG-570 Rx SIGNAL PATH Rx DIGITAL FILTER BLOCKS AD9361 Rx signal path passes downconverted signals (I The four blocks following the ADC in Figure 17 comprise the and Q) to the baseband receiver section. The baseband Rx digital filtering for the receive path.

  • Page 34: Digital Rx Block Delay

    UG-570 AD9361 Reference Manual Example—LTE 10 MHz Rx FIR In this example, the receiver is set to operate in an LTE 10 MHz The last digital filter in the Rx signal path is a programmable system with a 40 MHz reference clock used. All 128 FIR filter poly-phase FIR filter.

  • Page 35: Gain Control

    AD9361 Reference Manual UG-570 GAIN CONTROL Each receiver has its own gain table that maps a gain control OVERVIEW word to each of the variable gain blocks in Figure 19. A pointer AD9361 transceiver has several gain control modes that to the table determines the control word values sent to each enable its use in a variety of applications.

  • Page 36: Gain Control Threshold Detectors

    UG-570 AD9361 Reference Manual GAIN CONTROL THRESHOLD DETECTORS Figure 20 shows how the ADC overload detector processes signals and how the thresholds are used. AD9361 uses detectors to determine if the received signal is ADC SAMPLE VALUES overloading a particular block or if the signal has dropped below programmable thresholds.

  • Page 37: Settling Times

    INDEX GAIN INDEX GAIN INDEX GAIN (dB) GAIN INDEX (POINTER) Figure 21. Portion of the Analog Devices 2300 MHz Example Full Gain Table LMT MAX INDEX (0x0FD) INDEX 24 LPF INDEX LPF GAIN (0x10A AND 0x10D) (TABLE) TABLE LMT INDEX...

  • Page 38: Split Table Mode

    (and digital gain if it is enabled). This allows the index of 76(d). For the gain tables provided by Analog Devices, gain to be changed in the area of the receive path that is this leaves 24(d) indices left over for digital gain.
  • Page 39 AD9361 Reference Manual UG-570 The BBP can control manual gain in one of two ways. The default Alternatively, if the Use AGC for LMT/LPF Gain bit is set, the method uses SPI writes of the gain indices. Alternatively, the BBP AD9361 peak detectors determine where the gain changes.

  • Page 40: Slow Attack Agc Mode

    UG-570 AD9361 Reference Manual SLOW ATTACK AGC MODE SLOW ATTACK AGC GAIN UPDATE TIME Slow attack mode is intended for slowly changing signals such as When the average signal power exceeds a threshold, the gain does those found in some FDD applications, for example, WCDMA not necessarily change immediately.

  • Page 41: Overloads In Slow Attack Agc Mode

    AD9361 Reference Manual UG-570 OVERLOADS IN SLOW ATTACK AGC MODE (LMT or ADC) has tripped, setting the Prevent Gain Inc bit prevents the gain from increasing. In addition to the control loop discussed previously, the slow Like LMT and ADC overloads, the...

  • Page 42: Hybrid Agc Mode

    UG-570 AD9361 Reference Manual HYBRID AGC MODE index by the time the data portion of the signal arrives. The AGC also has an optional slow decay that allows the gain to increase if The hybrid AGC mode is the same as the slow AGC mode with the signal power decreases while the AGC is locking to an the exception that the gain update counter is not used.

  • Page 43: State 0: Reset

    AD9361 Reference Manual UG-570 STATE 0: RESET The Case #1 step size is typically larger than Case #2 which itself is typically larger than Case #3. The AGC remains in this state when the AD9361 is not in the Rx Table 21 shows the effects of various overloads when using a split state.

  • Page 44: State 2: Measure Power And Lock Level Gain Change

    UG-570 AD9361 Reference Manual STATE 2: MEASURE POWER AND LOCK LEVEL GAIN STATE 3: MEASURE POWER AND PEAK OVERLOAD CHANGE DETECT Upon entering State 2, the AGC waits for a time equal to Settling When the AGC enters State 3, it locks the gain. This state can Delay minus Energy Detect Count.

  • Page 45: State 5: Gain Lock And Measure Power

    AD9361 Reference Manual UG-570 STATE 5: GAIN LOCK AND MEASURE POWER forced to a fixed value). Optimize Gain and Set Gain both can reduce the time required for gain lock since they both use the When the AGC reaches State 5, the AGC locks the gain (if it was previous burst gain index information.
  • Page 46 UG-570 AD9361 Reference Manual When comparing the signal power with the energy lost threshold, Generally, the AGC is the best arbiter of when the gain should there is also a time factor as well. Each time the signal power unlock. However, in some situations, it may be advantageous for value updates, the AGC computes the difference between the the BBP to initiate an unlock condition.

  • Page 47: Custom Gain Tables

    Mixer Gm Index (d) Mixer Gm Index Gain (dB) Analog Devices supplies gain tables to use with the AD9361, but some applications require modifying those tables to optimize the RF performance (using an external LNA or creating 3 dB gain steps for example).
  • Page 48 Table 32 shows a small portion of an example full gain table. This Moving to the right again leads to the iLNA index. This is the is the same format as the Analog Devices supplied full gain table, internal LNA index, which controls LNA gain. iLNA Gain in dB is...

  • Page 49: Rf Dc Cal Bit

    In this case, set the RF DC Cal bit in Since the BBP controls the gain in the AD9361, it also can control the lowest index of the unique LMT gain. In Table 32, note that the RF DC Cal bit is set for Index 0 but not set for Indices 1 the gain of the external LNA.

  • Page 50: Received Signal Strength Indicator (Rssi)

    UG-570 AD9361 Reference Manual RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) If the Default RSSI Meas Mode bit is clear, then non-power-of-two OVERVIEW durations are possible per Equation 19. The four duration Given the wide variety of applications for which the AD9361 values are stored in Register 0x150 and Register 0x151.

  • Page 51: Rssi Preamble And Rssi Symbol

    The resulting registers. The RSSI Preamble value remains fixed and does not value is in dB and referenced to the input of the AD9361. If the continue to update unless the algorithm restarts. The RSSI...
  • Page 52 UG-570 AD9361 Reference Manual Table 35. Gain Step Calibration Register Values vs. LO Frequency LO Frequency Step Register Value Variable in Table 36, Table 37, Range (MHz) Step Description Value (dB) (hex) and Table 39 600 to 1300 Maximum LNA Gain...
  • Page 53 AD9361 Reference Manual UG-570 Program the LNA gain step words into the internal table. Table 37. Programming the LNA Gain Steps into the Internal Table Command Addr/Data Comment SPIWrite 143,61 //Write R1 and R2 internal LNA tables & start clock...
  • Page 54 UG-570 AD9361 Reference Manual Program the indirectly-addressable LNA gain difference words exactly as done in Step 5. Finally, program the error words back into the AD9361 as described in Table 40. In the processes and scripts shown previously, Rx1 is calibrated and then the error word results are programmed into Rx1 and Rx2. The resulting RSSI errors are expected to be within approximately 0.5 dB for Rx2 when using Rx1 error words.

  • Page 55: Transmit Power Control

    AD9361 Reference Manual UG-570 TRANSMIT POWER CONTROL ATTENUATION WORD UPDATE OPTIONS OVERVIEW The BBP can write attenuation words at any time using the AD9361 transceiver uses an accurate and efficient method ad9361_set_tx_attenuation function. There are two choices for of transmit power control (TPC) that involves a minimum of when the new attenuation word is implemented.

  • Page 56: Tx Power Monitor

    UG-570 AD9361 Reference Manual Tx POWER MONITOR transmitter are not operating simultaneously, the AD9361 OVERVIEW provides the ability to reuse the receiver circuitry by This section describes the Tx power monitor (TPM) circuit multiplexing the power detector into the receive path. The operation and features.

  • Page 57: Input Matching/Attenuation Network

    R1 to R3 and C1, as close as possible to the Figure 30 shows a measured TPM frequency response using the AD9361. Tx_MON inputs are DC biased and the C1 capacitor matching circuit and component values in Figure 29. The is an ac-coupling capacitor used to ac couple Tx_MON input.

  • Page 58: Tx Power Monitor Gain Control

    TPM Transimpedance amplifier (TIA) gain is automatically set high input signal is Tx LO. or low by the AD9361. Tx RSSI1 and Tx RSSI2 values in Register 0x06B, Register 0x06C, and Register 0x06D are compensated for gain changes.

  • Page 59: Tpm Dynamic Range

    AD9361 Reference Manual UG-570 TPM DYNAMIC RANGE EXAMPLE OF TxMON CONFIGURATION AND MEASUREMENT OF TPM TRANSFER FUNCTION TPM dynamic range can be maximized on the top end by minimizing total TPM gain, that is, Tx Mon gain = 0 dB and The following example is based on measured results using a = 0 dB.

  • Page 60: Tpm Test Mode

    UG-570 AD9361 Reference Manual The resulting measured TPM transfer characteristics are shown As Figure 33 shows, the TPM TIA gain is not compensated by in Figure 33. The dashed line is uncompensated for Tx Mon the Tx RSSI algorithm. The 9.5 dB compensation that results in TIA gain change at the threshold and it shows a transition at the solid line would occur in the baseband processor.

  • Page 61: Rf Port Interface

    AD9361 Reference Manual UG-570 RF PORT INTERFACE It is critical to have these interfaces working properly to achieve OVERVIEW data sheet performance levels. The main considerations are as The purpose of this section is to define the expected AD9361 follows: port impedance values and potential impedance matching •...

  • Page 62: Rx Signal Path Interface

    UG-570 AD9361 Reference Manual Rx SIGNAL PATH INTERFACE Given a single-ended operation mode, a positive side connection is delineated by the _P at the end of the Rx input AD9361 LNA devices (1A, 1B, 1C, 2A, 2B, 2C) are port name and a negative side connection is delineated by the functional for the full 70 MHz to 6.0 GHz receive frequency...
  • Page 63 AD9361 Reference Manual UG-570 Rx1A AND Rx2A SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1A AND Rx2A SERIES EQUVALENT DIFFERENTIAL IMPEDANCE –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 FREQUENCY (70MHz TO 6GHz) FREQUENCY (GHz) Figure 38. AD9361 Rx1A and Rx2A Input Differential Impedance FREQUENCY (GHz) Figure 39.
  • Page 64 UG-570 AD9361 Reference Manual Rx1B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 FREQUENCY (70MHz TO 6GHz) FREQUENCY (GHz) Figure 40. AD9361 Rx1B Input Differential Impedance FREQUENCY (GHz) Figure 41.
  • Page 65 AD9361 Reference Manual UG-570 Rx1C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx1C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 FREQUENCY (70MHz TO 6GHz) FREQUENCY (GHz) Figure 42. AD9361 Rx1C Input Differential Impedance FREQUENCY (GHz) Figure 43.
  • Page 66 UG-570 AD9361 Reference Manual Rx2B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx2B SERIES EQUVALENT DIFFERENTIAL IMPEDANCE –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 FREQUENCY (70MHz TO 6GHz) FREQUENCY (GHz) Figure 44. AD9361 Rx2B Input Differential Impedance FREQUENCY (GHz) Figure 45.
  • Page 67 AD9361 Reference Manual UG-570 Rx2C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE Rx2C SERIES EQUVALENT DIFFERENTIAL IMPEDANCE –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 FREQUENCY (70MHz TO 6GHz) FREQUENCY (GHz) Figure 46. AD9361 Rx2C Input Differential Impedance FREQUENCY (GHz) Figure 47.
  • Page 68 UG-570 AD9361 Reference Manual From a design flexibility viewpoint, the following Rx path The balun/filter single-ended port is impedance matched with a impedance matching strategy is preferred. simple PII network. The balun/filter differential port is impedance matched with either a DC-blocked differential PII •...

  • Page 69: Tx Signal Path Interface

    AD9361 Reference Manual UG-570 Tx SIGNAL PATH INTERFACE Load-pull based impedance matching is very simple. The focus is on developing the preferred load impedance at the Tx output AD9361 transmit path covers a full 70 MHz to 6.0 GHz ball pads. This matching technique is quite different from the transmit frequency range and the 2 Tx outputs exhibit similar small-signal techniques utilized for the Rx input.
  • Page 70 UG-570 AD9361 Reference Manual TXA_N 1.3V TX OUTPUT TXA_P Figure 51. AD9361 Tx Output Differential Interface Configurations 1.3V TXA_N 1.3V TX OUTPUT TXA_P 1.3V Figure 52. AD9361 Tx Output Differential Interface Configurations 1.3V TXA_N 1.3V TX OUTPUT TXA_P 1.3V Figure 53.

  • Page 71: Factory Calibrations

    AD9361 Reference Manual UG-570 FACTORY CALIBRATIONS Tx RSSI (Tx MONITOR) OVERVIEW If the power detector is used, at minimum, a single point Tx Factory calibrations are necessary to limit the amount of RSSI measurement must be made to correlate the absolute variation seen across a large quantity of circuit boards.

  • Page 72: Rx Gm/Lna Gain Step Calibration

    UG-570 AD9361 Reference Manual Rx GM/LNA GAIN STEP CALIBRATION Tx POWER OUT VS. Tx ATTENUATION AND Tx POWER OUT VS. CARRIER FREQUENCY The gain of the LNA and mixer stages inside the AD9361 varies over temperature and frequency. This calibration is a onetime...

  • Page 73: Control Output

    Some of the signals are helpful in a production system while Some internal signals are available on more than one some others are useful for debug. In either case, Analog Devices combination of Control Output Pointer and Control Output recommends connecting the...

  • Page 74: Description Of Control Output Signals

    Rx quadrature, and gain step calibrations. After one these calibrations completes, the Cal Done signal transitions Once the BBP initiates a calibration on the AD9361, the BBP high. From that point on, while any of the previously listed should not execute additional code until the calibration calibrations runs, Cal Done is low, returning high at the completes.

  • Page 75: 0X035 = 0X01 (Pll Lock)

    AD9361 Reference Manual UG-570 Control Output 6 (Tx CP Cal Done) 0x035 = 0x02 (CALIBRATION BUSY) When the AD9361 powers up into the sleep state, this signal Control Output 7 (BB DC Cal Busy) is low. It transitions high after a Tx charge pump calibration Normally low.

  • Page 76: 0X035 = 0X04 (Rx Gain Control)

    UG-570 AD9361 Reference Manual Control Output 4 (CH1 Sm ADC Ovrg) Control Output 1 (CH2 Energy Lost) This signal transitions high if a small ADC overload occurs. This signal is normally low and applies only to the fast AGC. It The signal will stay high until the gain changes.

  • Page 77: 0X035 = 0X09 (Rxon, Txon, Rssi)

    AD9361 Reference Manual UG-570 Control Output 3 (CH2 Stronger Signal) 0x035 = 0x0A (DIGITAL OVERFLOW) See 0x035 = 0x05 Control Output 0. Control Output 7 (CH1 Tx Int3 Overflow) This signal is high if the Tx Int3 filter overflows. If the overflow Control Output 2 (CH2 Gain Lock) condition stops, the signal goes low.

  • Page 78: 0X035 = 0X0D (Tx Quadrature And Rf Dc Calibration Status)

    FIR outputs is valid. The time the signal remains high is Same as Control Output 5 but applies to Tx2 dependent on the internal clock rates of the AD9361. For the 0x035 = 0x0E (Rx QUADRATURE AND BB DC standard customer software LTE 10 MHz profile, the signal is CALIBRATION STATUS) high for approximately 65 ns.

  • Page 79: 0X035 = 0X13 (Gain Control, Power Word Ready)

    AD9361 Reference Manual UG-570 Control Output 3 (CH1 ADC Power Ready) 0x035 = 0x15 (DC OFFSET TRACKING) If ADC power is used for AGC power measurements, this signal Control Output 7 (CH1 SOI Present) will pulse high when a new power word is ready. The...

  • Page 80: 0X035 = 0X17 (Gain Control)

    UG-570 AD9361 Reference Manual 0x035 = 0x17 (GAIN CONTROL) Control Output 3 Through Control Output 0 (Tx Syn CP Cal[3:0]) Control Output 7 (CH2 Gain Lock) These signals represent the state of the transmitter charge pump See 0x035 = 0x08 Control Output 2.

  • Page 81: 0X035 = 0X1E (Gain Control, Temp Sense Valid, Auxadc Valid)

    AD9361 Reference Manual UG-570 0x035 = 0x1E (GAIN CONTROL, TEMP SENSE Control Output 1 (Temp Sense Valid) VALID, AUXADC VALID) This signal changes state when the temperature sensor word is valid. The BBP can manually start a temperature measurement Control Output 7 (CH1 Low Thresh Exceeded)

  • Page 82: Auxadc/Auxdac/Gpo/Temp Sensor

    This section describes operation of the auxiliary features disabled when the device is first powered up. available in the AD9361. These features help simplify system In certain applications, it is desirable to delay the AuxDAC tasks and lower overall system cost. They include two 10-bit transition after the enable signal transitions.

  • Page 83: Auxadc

    AD9361 Reference Manual UG-570 AuxADC Equation 22 determine the AuxADC clock frequency and the decimation rates. The AuxADC is a 12-bit auxiliary converter with an input level range 0 V to 1.3 V with an adjustable conversion time. The The AuxADC output is read from Register 0x1E (D7:D0) and Register 0x1F (D3:D0).

  • Page 84: Internal Temperature Sensor

    UG-570 AD9361 Reference Manual INTERNAL TEMPERATURE SENSOR temperature sensor periodically takes temperature readings as per Equation 24. If temperature measurements are to be The AuxADC can also be used to measure the internal performed manually (Bit D0 of Register 0x0D is clear) then the temperature of the DUT.

  • Page 85: General Purpose Output Control

    AD9361 Reference Manual UG-570 GENERAL PURPOSE OUTPUT CONTROL Some applications have a need to insert a delay between the DUT state transitions and GPO pin toggles. To accommodate AD9361 has four GPO pins that can be setup using the these needs, there are GPO registers that can be programmed to ad9361_gpo_setup function.
  • Page 86 UG-570 AD9361 Reference Manual Figure 58 shows the timing of the GPOs and AuxDAC1 based GPO Voltage Level, Drive Strength on the code written in Table 47 when the device transitions The VDD_GPO pin (B8) which has a voltage range of 1.3 V to from alert to receive.

  • Page 87: Baseband Synchronization

    AD9361 Reference Manual UG-570 BASEBAND SYNCHRONIZATION MIMO systems requiring more than two input or two output OVERVIEW channels, multiple AD9361 devices and a common reference For broadband wireless access (BWA) systems, multi input- oscillator are required. The AD9361 provides the capability to...

  • Page 88: Procedure

    UG-570 AD9361 Reference Manual PROCEDURE Connect all AD9361 clock inputs to a common buffered cannot be used if the 1/2× or 1/4× options are selected for the internal BBPLL REF_CLK. Note that the SYNC_IN reference using the XTALN pin as shown in Figure 59 for proper synchronization.

  • Page 89: Synchronization Verification

    AD9361 Reference Manual UG-570 SYNCHRONIZATION VERIFICATION DATA_CLK BOARD 1 DATA_CLK BOARD 2 Data synchronization can be verified by observing the SYNC_IN INPUT PULSE DATA_CLK signal of each chip simultaneously using an oscilloscope. The waveforms will overlap after successfully completing the sync procedure. Similarly, the CLK_OUT pin on each device (when enabled) can be monitored to determine if the ADC clocks are synchronized.

  • Page 90: Digital Interface Specification

    UG-570 AD9361 Reference Manual DIGITAL INTERFACE SPECIFICATION When CMOS mode is used: OVERVIEW • Single ended-CMOS logic compatibility is maintained. This section defines the parallel data ports and the serial • Either one or both data ports may be utilized. Using two peripheral interface (SPI) that enable the transfer of data and ports allows for higher data throughput.

  • Page 91: Cmos Mode Data Path And Clock Signals

    For applications that do not require fast effective data rates, a single port can be used to minimize RX_FRAME connections to the AD9361. The data path interface consists of RX_FRAME is driven by the AD9361 to identify valid data for the signals described in the following sections.

  • Page 92: Cmos Maximum Clock Rates And Signal Bandwidths

    In this mode (called FDD independent control mode), TX_FRAME signals are used to determine valid data by the the BBP independently controls the Tx function, which can BBP and the AD9361, respectively. The FB_CLK signal is used result in power consumption savings. to sample this input.

  • Page 93: Single Port Half Duplex Mode (Cmos)

    AD9361 Reference Manual UG-570 transfer starts when the ENABLE signal pulses (or goes high), SINGLE PORT HALF DUPLEX MODE (CMOS) and the end of the data transfer is marked but another pulse on Single port half duplex mode is used in applications requiring the ENABLE line (or when it returns low).

  • Page 94: Single Port Tdd Functional Timing (Cmos)

    These unused slots are ignored by and 2R1T configurations are shown to illustrate that their the AD9361. For example, in a 2R1T system with only Tx timing is identical to the 2R2T configuration. Behavior with...
  • Page 95 AD9361 Reference Manual UG-570 1R1T, DDR, TDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x2C DATA _CLK RX _FRAME R1_I[11:0] R1_Q[11:0] R1_I[11:0] R1_Q[11:0] R1_I[11:0] R1_Q[11:0] P0_D[11 :0] P1_D[11 :0] 1R1T, DDR, TDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x0C...
  • Page 96 UG-570 AD9361 Reference Manual 1R1T, DDR, TDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x2C FB_CLK TX _FRAME T1_I[11:0] T1_Q[11:0] T1_I[11:0] T1_Q[11:0] T1_I[11:0] T1_Q[11:0] P0_D[11 :0] P1_D[11 :0] 1R1T, DDR, TDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x0C...

  • Page 97: Single Port Full Duplex Mode (Cmos)

    These unused slots are ignored by signifies the end of data transfer. the AD9361. As an example, for a 2R1T system using Transmit The Rx_FRAME and Tx_FRAME signals indicate the Channel 1, the transmit burst would have four unused slots, as beginning of a set (frame) of data samples.
  • Page 98 UG-570 AD9361 Reference Manual AD9361 DATA_CLK FEEDBACK CLK GEN RX_FRAME P0_D[5:0] DATA DATA TX_FRAME P0_D[11:6] DATA DATA FB_CLK TXNRX CTRL CTRL ENABLE Figure 67. Single Port Full Duplex Mode Rev. A | Page 98 of 128...

  • Page 99: Single Port Fdd Functional Timing (Cmos)

    AD9361 Reference Manual UG-570 SINGLE PORT FDD FUNCTIONAL TIMING (CMOS) The timing diagrams in Figure 68 and Figure 69 illustrate the relationship among the bus signals in single port FDD mode. Note that because 2R1T and 1R2T systems follow the 2R2T timing diagrams, they are omitted from Figure 68 and Figure 69.

  • Page 100: Dual Port Half Duplex Mode (Cmos)

    TXNRX is driven high, the ENSM changes the bus to the mode, and data direction is determined by which channel is transmit direction (data transferred from BBP to AD9361). active: transmit or receive. Each bus can be operated as either During a transmit burst, both ports (P0_D[11:0] and SDR or DDR in this configuration.

  • Page 101: Dual Port Tdd Functional Timing (Cmos)

    AD9361 Reference Manual UG-570 The data samples are carried in two’s complement format, with with only a single channel used, the disabled channel’s I-Q pair D[11] as the numerically most significant bit and D[0] as the in each data group is unused. As an example, for a 2R1T system least significant bit.
  • Page 102 UG-570 AD9361 Reference Manual 1R1T, DDR, TDD, DUAL PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x08 FB_CLK TX _FRAME T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0] T1_I[11:0] P0_D[11:0] P1_D[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] T1_Q[11:0] 2R2T, DDR, TDD, DUAL PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x08...

  • Page 103: Dual Port Full Duplex Mode (Cmos)

    Tx and Rx data negative value is 0x800. between the BBP and the AD9361. For this mode, each data bus The I and Q data samples are carried on the same data bus in must operate at twice the speed of the dual port TDD mode to each direction.

  • Page 104: Dual Port Fdd Functional Timing (Cmos)

    UG-570 AD9361 Reference Manual DUAL PORT FDD FUNCTIONAL TIMING (CMOS) The timing diagrams in Figure 74 and Figure 75 illustrate the relationship among the bus signals in dual port full duplex mode. Note that because 2R1T and 1R2T systems follow the 2R2T timing diagrams, they are omitted from Figure 74 and Figure 75.

  • Page 105: Data Bus Idle And Turnaround Periods (Cmos)

    The P0_D[11:0] and P1_D[11:0] bus signals are usually actively shows the relationship between the data clocks and the driven by the BBP or by the AD9361. During any idle periods, hardware control inputs. Figure 77 show the relationship the data bus values are ignored by both components. Both among all other parameters.

  • Page 106: Lvds Mode Data Path And Clock Signals

    UG-570 AD9361 Reference Manual AD9361 LVDS interface facilitates connecting to custom LVDS MODE DATA PATH AND CLOCK SIGNALS ASICs and FPGAs that have LVDS capability. LVDS interfaces The following information describes operation of the AD9361 are typically used when a system needs superior switching...

  • Page 107: Lvds Mode Data Path Signals

    (50% duty cycle). The Rx_FRAME and Tx_FRAME signals are used to determine Rx_D[5:0] valid data by the BBP and the AD9361, respectively. The FB_CLK signal is used to sample this input. Rx_D[5:0] is a differential LVDS data bus consisting of six differential pairs.

  • Page 108: Revision History 6/15-Rev. 0 To Rev. A Change To Table 50

    UG-570 AD9361 Reference Manual TXNRX mode in which the TXNRX signal can be redefined as TxON, a direct hardware control input to the ENSM that controls the Tx TXNRX is driven from the BBP to the AD9361 and provides function. In this mode (called FDD independent control mode),...

  • Page 109: Dual Port Full Duplex Mode (Lvds)

    I-Q pair in each data group is unused. These with the first word being 0x20 and the second word being 0x00. unused slots are ignored by the AD9361. As an example, for a Tx_D[5] is the most significant bit and Tx_D[0] is the least 2R1T system using Tx channel 1, the transmit burst would have significant bit in each word.
  • Page 110 UG-570 AD9361 Reference Manual 1R1T, DDR, FDD, LVDS, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x10 DATA_CLK_P DATA_CLK_N RX_FRAME_P RX_FRAME_N R_I[11:6] R_Q[11:6] R_I[5:0] R_Q[5:0] R_I[11:6] R_Q[11:6] R_I[5:0] R_Q[5:0] R_I[11:6] R_Q[11:6] R_I[5:0] R_Q[5:0] RX_D[5:0]_P R_I[11:6] R_Q[11:6] R_I[5:0] R_Q[5:0] R_I[11:6] R_Q[11:6] R_I[5:0]...

  • Page 111: Data Path Timing Parameters (Lvds)

    AD9361 Reference Manual UG-570 The following bits are not supported in LVDS mode: • Swap Ports—In LVDS mode, P0 is Tx and P1 is Rx. This configuration cannot be changed. • Single Port Mode —Both ports are enabled in LVDS mode.
  • Page 112 UG-570 AD9361 Reference Manual DATA_CLK_P DATA_CLK_N DDDV RX_FRAME_P RX_FRAME_N DDRX RX_D[5:0] FB_CLK_P FB_CLK_N TX_FRAME_P TX_FRAME_N TX_D[5:0] Figure 81. Data Port Timing Parameter Diagrams—LVDS Bus Configuration Rev. A | Page 112 of 128...

  • Page 113: Serial Peripheral Interface (Spi)

    SPI_CLK by both the BBP The SPI bus provides the mechanism for all digital control of and the AD9361. SPI_DI (or SPI_DIO) carries the control field the AD9361. Each SPI register is 8-bit wide, and each register from BBP to the AD9361...
  • Page 114 UG-570 AD9361 Reference Manual [D11:D10]—Bits[11:10] of the instruction word are unused. Example: MSB-First Multibyte Transfer [D9:D0]—Bits[9:0] specify the starting byte address for the data To complete a 4-byte write, starting at Register 0x02A in MSB transfer during Phase 2 of the IO operation.
  • Page 115 AD9361 Reference Manual UG-570 SPI_ENB SPI_CLK SPI_DI SPI_DO WRITE TO REGISTER 0x15A, VALUE = 0x55 Figure 82. Nominal Timing Diagram, SPI Write SPI_ENB SPI_CLK SPI_DI SPI_DO READ REGISTER 0x15A, VALUE = 0x55 Figure 83. Nominal Timing Diagram, SPI Read Table 53 lists the timing specifications for the SPI bus. The relationship between these parameters is shown in Figure 84. This diagram shows a 3-wire SPI bus timing diagram with these parameters marked.

  • Page 116: Additional Interface Signals

    RESETB is an input signal allowing asynchronous hardware BBP to directly control the time that the gain setting changes. reset of the AD9361. A logic low applied to this pin resets the CTRL_OUT[7:0] device (all SPI registers are reset to default settings and the The CTRL_OUT pins are eight programmable digital output device is placed in SLEEP mode).

  • Page 117: Power Supply And Layout Guide

    Layer 6. The RF traces on the outer layers need to be controlled • Power management and system noise considerations impedance to get the best performance from the AD9361. • Power distribution to all the different power domains 1 ounce copper is used for all the inner layers in this board. The outer layers use 1.5 ounce copper so that the RF traces are less...

  • Page 118: Rf Transmission Line Layout

    This ensures good signal integrity for the SMA launch. See the RF Port Interface section for more information on the RF matching issues associated with the AD9361. Figure 86. RF Match Structures on Rx and Tx on FMComms2 Board Rev. A...

  • Page 119: Fan-Out And Trace Space Guidelines

    AD9361 Reference Manual UG-570 FAN-OUT AND TRACE SPACE GUIDELINES 12 mil keep out. The spacing between the BGA lands to the pin escape via is 22 mils. Once the signal is on the inner layers, a AD9361 is in a 10 mm × 10 mm 144-pin BGA package.

  • Page 120: Component Placement And Routing Guidelines

    1.2 V to 2.5 V. This voltage controls the voltage levels of VDD_INTERFACE for proper functioning. To reset the the digital interface of the AD9361. To operate the digital part, pull the RESETB ball low. interface in LVDS mode, supply 1.8 V or 2.5 V to the VDD_INTERFACE supply.
  • Page 121 Noise Floor to achieving the best performance from the AD9361. Any spurs It is beneficial to have a switching regulator with a low noise or noise from the power supply within a 1 MHz span will floor.
  • Page 122 UG-570 AD9361 Reference Manual Maximum Output Capacitance Output Noise Spectrum In switching regulators with limitation for the maximum Figure 89 shows the output spectrum of the ADP5040 switching allowable output capacitance, it is important to consider the regulator up to 1 MHz. This span is important, as the...
  • Page 123 AD9361 Reference Manual UG-570 the synthesizer output is divided which also reduces the noise Effects on Phase Noise Due to Noise on the Power Supply spectrum. Conversely, the highest frequency designs require the Figure 90 shows the effects of power supply noise on the phase lowest amount of power supply noise because the divide ratios noise of the transmitter local oscillator.

  • Page 124: Power Distributions For Different Power Supply Domains

    UG-570 AD9361 Reference Manual POWER DISTRIBUTIONS FOR DIFFERENT POWER SUPPLY DOMAINS AD9361 has 17 power supply balls. These balls power up different circuits on the part. Table 55 shows the ball number, the ball name, the recommended routing technique for that ball from the main 1.3 V analog supply plane and a brief description of the block it powers up in the chip.
  • Page 125 AD9361 Reference Manual UG-570 Rx and Tx Synthesizer Supplies Tx Balun DC Feed Supplies The power supply noise rejection on the VDDA1P3_ Each transmitter requires 150 mA of current that the DC feed Rx_SYNTH and VDDA1P3_Tx_SYNTH power domains is of the balun supplies. To reduce switching transients when very low.

  • Page 126: Rx Lo Frequency Deviations Due To Power Supply Transients

    UG-570 AD9361 Reference Manual Rx LO FREQUENCY DEVIATIONS DUE TO POWER The blue trace in Figure 93 shows the voltage transient on the 1.3 V line when the transmitters turn ON. The magenta trace is SUPPLY TRANSIENTS the Vtune voltage of the Tx VCO that is probed on the Tx EXT...
  • Page 127 AD9361 Reference Manual UG-570 VOLTAGE TRANSIENT ON THE 1.3V LINE WHEN THE TRANSMITTERS TURN ON VTUNE VOLTAGE OF THE RX VCO THAT IS PROBED ON THE RX EXT LO LINE VTUNE VOLTAGE OF THE TX VCO THAT IS PROBED ON THE TX EXT LO LINE Figure 93.

  • Page 128: Rev. A

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