Analog Gain Control Api Programming - Analog Devices ADRV9005 Reference Manual

Reference Manual ADRV9001
RECEIVER GAIN CONTROL
Figure 173. Immediate Gain Attack Causing Delayed Gain Recovery
To prevent this happening and to maintain a perfectly periodic gain recovery event, the gain attacks are prevented from happening towards the
end of the gain update counter state, as shown in Figure 172. If a gain attack happens in this period, it is delayed until the start of the next
gain update counter state. This can cause gain attacks to be held off for up to 2× SLS + 5 delay; therefore, it is recommended to keep the SLS
delay as short as possible to minimize the gain attack delay. Note that it is possible to disable this blocking feature, thus allowing gain attacks
to occur anywhere within the gain update counter state. However, the periodicity of the gain recovery event is no longer guaranteed as gain
attacks towards the end of the gain update counter state causes the gain recovery event to be delayed, as shown in Figure 173.
At the expiry of the gain update counter (or low underrange interval in the "fast recovery" mode), all measurement blocks are reset, and
any peak detector counts are reset back to zero. When the receiver is enabled, the counter begins. This might mean that its expiry is at
an arbitrary phase to the slot boundaries of the signal. The expiry of the counter is aligned to the slot boundaries by setting the parameter
enableSyncPulseForGainCounter. While this bit is set, the AGC monitors a DGPIO pin to find a synchronization pulse. This pulse causes the
reset of the counter at this point; hence, if the user supplies at the DGPIO pulse time aligned to these slot boundaries, the expiry of the counter
is aligned to the slot boundaries. Any of DGPIO pins 0 to 15 is used for this purpose. Note this feature is not supported currently.
For example, considering the 100 µs gain update period and a 184.32 MHz AGC clock, 18,432 AGC clocks exist in the gain update period.
Gain Update Period (AGC Clocks) = 184.32 MHz × 100 μs = 18,432
As noted, the full gain update period is the sum of the gainUpdateCounter, slowLoopSettlingDelay, and a number of AGC clock cycles. If the
slowLoopSettlingDelay is set to 4, set the gain update counter to 18,423 from the following calculation.
Gain Update Period (AGC Clocks) = gainUpdateCounter + slowLoopSettlingDelay +5
Gain Update Period (AGC Clocks) = 18,423 + 4 + 5 = 18,432
When the receiver is enabled, attackDelay_us keeps the AGC inactive for a number of the AGC clock cycles. This means the user can specify
one delay for AGC reaction when entering the receive mode and another after the gain change occurs (slowLoopSettlingDelay).

ANALOG GAIN CONTROL API PROGRAMMING

As mentioned earlier, the Rx gain control mode is configured as the MGC or AGC mode. In both the modes, the API function
adi_adrv9001_Rx_GainControl_Configure() is used to configure the gain control blocks, such as the peak detectors and power detector for
a specific channel. These detectors are used not only in the AGC mode but also in the MGC mode to feed important information. This API
function also configures the DGPIO pins to retrieve the signal detectors information.
Note that although signal detector information is critical for the MGC mode, it can also be obtained in the AGC mode for observation and
debugging.
The next section discusses the composition of the gain control configuration structure adi_adrv9001_GainControlCfg_t in detail. Once it is
configured, the desired gain control mode can be enabled using adi_adrv9001_Rx_GainControl_Mode_Set() API.
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