Product Highlights; Adrv9002 - Analog Devices ADRV9005 Reference Manual

Reference Manual

PRODUCT HIGHLIGHTS

ADRV9002

The ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery-powered radio
equipment. It can operate in both the frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates from 30
MHz to 6000 MHz, which covers the very high frequency (VHF), licensed and unlicensed cellular bands, and industrial, scientific, and medical
(ISM) bands. The IC supports both narrowband and wideband standards up to 40 MHz bandwidth on both a receiver and transmitter.
The transceiver consists of direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter
sub-system includes DC offset correction, quadrature error correction (QEC), and programmable digital filters, which eliminate the need for
these functions in the digital baseband. In addition, several integrated auxiliary functions such as an auxiliary analog-to-digital converter (ADC),
auxiliary digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) provide additional monitoring and control capability.
The fully-integrated phase locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter,
receiver, and clock sections. Careful design and layout techniques provide the isolation required in high performance mobile radio applications.
All integrated voltage controlled oscillator (VCO) and loop filter components minimize the external component count. The local oscillators (LOs)
have flexible configuration options and include fast lock modes.
The transceiver includes low-power sleep and monitor modes to save power, which extends the battery life of portable devices while monitoring
communication.
The fully-integrated low power DPD is supported by the ADRV9002. It can linearize wideband and narrowband signals to enable the
linearization of high efficiency power amplifiers. In use cases where the integrated DPD is used, main receivers are used as a power amplifier
observation path.
The power supply for the ADRV9002 is distributed across four or five different voltage supplies: 2 or 3 analog and 2 digital. The analog
supplies are 1.8 V, 1.3 V, and 1.0 V (in internal low dropout (LDO) bypass mode). The 1.3 V domain directly feeds some blocks and internal
LDO regulators for some functions as well for maximum performance. The 1.8 V analog domain optimizes transmitter and auxiliary converter
performance. The digital processing blocks are supplied by a 1.0 V source. In addition, a 1.8 V supply is used to supply all GPIO and interface
ports that connect with the baseband processor.
High and low data rate interfaces are supported using configurable complementary metal oxide semiconductor (CMOS) or low voltage
differential signaling (LVDS) synchronous-serial interface (SSI) choice.
The core of the ADRV9002 is controlled through a standard 3-wire or 4-wire serial port. All software control is communicated through this
interface. There is also a control interface that uses GPIO lines to provide hardware control to and from the device. These pins can be
configured to provide dedicated sets of functions for different application scenarios.
The block diagram in Figure 2
each block with setup and control details.
Bandwidth and Sample Rate Support
The ADRV9002 supports the reception and transmission of channels up to 40 MHz bandwidth. The available standard sample rates are 24 kHz
(typically for narrowband FM waveforms), 144 kHz, and 288 kHz (typically for terrestrial trunked radio (TETRA) signals), and 1.92 MHz, 3.84
MHz, 7.68 MHz, 15.36 MHz, 23.04 MHz, 30.72 MHz, and 61.44 MHz (typically for long-term evolution (LTE) signals).
In addition, the ADRV9002 supports an almost continuous range of sample rates between 24 kHz and 61.44 MHz. It does not support some
sample rates due to internal clocking constraints.
The sample rate is scaled by enabling or disabling decimation or interpolation filters in the digital signal chain.
Data Interfaces
The ADRV9002 supports both the CMOS and LVDS electrical interfaces for its data lanes. All data lanes support both the electrical interfaces,
but do not support their concurrent operation. Each transmit and receive channel has a dedicated set of lanes to transfer the information.
The CMOS bus speed is limited to 80 MHz. The CMOS-SSI electrical interface has two operating modes. For low sample rates, the mode has
32 bits (16 bits of I and Q data each) that are serialized over a single lane with two additional lanes total required for a clock (single data rate
(SDR) or double data rate (DDR)) and a frame synchronization signal, which supports a maximum sample rate of 2.5 MHz.
analog.com
shows a high level view of the functions in the ADRV9002. The subsequent sections of this document describe
ADRV9001
Rev. A | 9 of 377