Analog Devices ADRV9005 Reference Manual page 92

Reference Manual ADRV9001
MICROPROCESSOR AND SYSTEM CONTROL
Hold Time Between RX_ENABLE Rising Edge and RX_ENABLE Falling Edge
After a RX_ENABLE rising edge, its falling edge must come after a delay of at least t or t (if controlling LNA power).
RxEnaRise2AnaOn RxEnaRise2On
To actually receive data, the channel must be on for a duration longer than its propagation delay. Achieve this either by making sure that
RX_ENABLE is high for longer than the propagation delay or by ensuring the t is longer than t . Figure 76 describes this scenario.
RxEnaHold RxPD
Figure 76. Minimum Hold Time Between RX_ENABLE Rising Edge and RX_ENABLE Falling Edge
Timing Parameters with Power Savings Modes
The ADRV9001 offers several channel power savings modes (Power Saving Mode 0, 1, and 2) that trade off better power savings with longer
transition time to turn on and turn off a transmit or receive channel. For more details about power saving modes, see the Power Savings and
Monitor Mode section. To take advantage of the power saving modes, set the timing parameters appropriately.
Note that the minimum guard time discussed previously does not consider the time taken to power down the transmit or receive analog by
assuming it is insignificant. But it is highly recommended to allow extra time to make sure the analog power-up happens only after the analog
power-down is fully completed. The analog power-down time is usually much less than the analog power-up time.
Figure 77. Channel Power-Up and Power-Down Sequences in Different Power Savings Modes
Figure 77 shows the sequence of events to power up or down a transmit or receive channel in the various channel power savings modes.
In Power Savings Mode 1 and 2, the enableRiseToAnalogOnDelay is used to power up additional entities powered down at the end of
the previous frame. (Note that in Power Savings Mode 1 and 2, PLL is powered down at the end of the previous frame. Therefore, when
it is turned on at the start of the new frame, PLL tuning is required.) Thus, set the enableRiseToAnalogOnDelay long enough to allow
the power up procedures to complete. If the additional power-up procedures in Power Savings Mode 2 take t to complete,
PowerUpPSM2
the ADRV9001 prevents the system from entering the Power Savings Mode 2, unless enableRiseToAnalogOnDelay is set greater than
t . The same is true for Power Savings Mode 1. The ADRV9001 prevents the system from entering Power Savings Mode 1, unless
PowerUpPSM2
enableRiseToAnalogOnDelay is set greater than t . In Power Savings Mode 0, which is the default mode, there are no additional
PowerUpPSM1
power-up procedures. Thus, there are no additional restrictions on enableRiseToAnalogOnDelay other than those already specified in earlier
sections.
If switching dynamically between several power savings modes, set the enableRiseToAnalogOnDelay to satisfy the restrictions of the highest
power savings mode. Figure 77 shows that there is a longer idle time when switching to a lower power savings mode. The parameter
enableRiseToAnalogOnDelay cannot be changed dynamically. Thus, the timing of the TX_ENABLE/RX_ENABLE rising edge relative to the on
air time must also remain the same even when dynamically switching between different power savings modes.
In certain use cases, when the transmit and receive are using the same LO, but at different frequencies, if the transition time between the
transmit and receive frames are always long enough, PLL tuning at the start of the frame. This is not related to any specific power saving mode
and PLL tuning happens even in Power Saving Mode 0. Figure 78 shows the timing diagram.
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