External Lo Port Impedance Matching Power Supply Optimization - Analog Devices ADRV9005 Reference Manual

Reference Manual
POWER-SUPPLY RECOMMENDATIONS
Table 125. Instructions Explaining How to Handle ADRV9001 Unused Pins (Continued)
Pin No.
N6
N7, N8, P1, P14
N9
N10
N11
N12
N13
N14
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
POWER SUPPLY OPTIMIZATION
Power Supply Optimization Options
Make optimizations in the power supply section to reduce the number of individual rails and filters to save on BOM and space. One possible
optimization is the combination of different rails of the same voltage domain. In doing this, it is important to identify the aggressor and victim
rails to decide what to combine and what to keep shielded with an FB filter.
Table 126. Victim and Aggressor Rails
Rail Name
VANNA1_1P3
VANNA2_1P3
VCONV_1P3
For this experiment, the combined rails are as follows. This reduces the number of caps and ferrite beads needed on the board.
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Type Mnemonic
Input TX2_DCLK_IN-
Input VSSD
Input TX1_DCLK_IN-
Input TX1_DCLK_IN+
Output RX1_QDATA_OUT+
Output RX1_QDATA_OUT-
Output RX1_STROBE_OUT+
Output RX1_STROBE_OUT-
Input TX2_STROBE_IN+
Input/Output TX2_STROBE_IN-
Input TX2_QDATA_IN-
Input TX2_QDATA_IN+
Input TX2_IDATA_IN+
Input TX2_IDATA_IN-
Input TX1_IDATA_IN-
Input TX1_IDATA_IN+
Input TX1_QDATA_IN+
Input TX1_QDATA_IN-
Input/Output TX1_STROBE_IN-
Input TX1_STROBE_IN+
Unused Instructions
Do not connect.
Not applicable.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Do not connect.
Rail Type
Victim
Victim
Aggressor
ADRV9001
Rev. A | 320 of 377