Data Interface; General Description; Electrical Specification; Changes To Table 24 - Analog Devices ADRV9005 Reference Manual

Reference Manual

DATA INTERFACE

GENERAL DESCRIPTION

This document defines the synchronous-serial interface (SSI), which transfers the data between the ADRV9001 and a baseband processor.
The ADRV9001 SSI consists of two receive channels and two transmit channels. The channels are independent and can be configured
either as complementary metal oxide semiconductors (CMOS) signals (CSSI) for applications that have narrow RF signal bandwidths and low
data-rate, or as low voltage differential signaling (LVDS) signals (LSSI) for applications that require high-speed, low noise, and longer distance
data transfer.
The CSSI supports the following two modes of operation and can be operated as either single data rate (SDR) or double data rate (DDR) data
transfer, and the maximum clock frequency is 80 MHz:
One-lane data mode, I/Q data, or other format data are serialized onto one single lane.
►
Four lanes data mode, which is valid only when the ADRV9001 transmits or receives I/Q samples, and the I/Q samples are 16 bits wide. In
►
the four-lane data mode, each sample is split into 8 bit blocks of data and sent over one data lane.
The LSSI also supports the following two modes of operation, and always operates in DDR data transfer. The maximum clock frequency is
491.52 MHz:
I/Q in one lane (one-lane mode)
►
With I-Q data samples of 16 bits (total of 32 bits for each transfer)
►
I/Q in separate lanes (two-lane mode)
►
With I and Q data samples of 16 bits
►
With I and Q data samples of 12 bits
►
The ADRV9001 SSI has various and flexible work modes to support many kinds of system scenarios. Choose the appropriate work modes
according to the interface sample/symbol rate and bit width.
sample rate.
Table 24. ADRV9001 SSI Work Modes
Data Lanes Per
SSI Modes Channel
CSSI 1-Lane 1
CSSI 1-Lane 1
1
CSSI 1-Lane 1
CSSI 4-Lane 4
CSSI 4-Lane 4
2
LSSI 1-Lane 1
LSSI 2-Lane 2
2, 3
LSSI 2- Lane 2
LSSI 2-Lane 2
2, 4
LSSI 2- Lane 2
1
ADRV9001 data port transmit/receive data symbols, see the section
2
Currently not implemented.
3
For user's LVDS data lane rate limitation applications, the receive samples are rounded from 16 bits to 12 bits. The transmit samples are extended from 12 bits to 16 bits.
4
For user's LVDS data lane rate limitation applications, the receive samples are rounded from 16 bits to 12 bits. The transmit samples are extended from 12 bits to 16 bits.
The following sections detail the signals that make up the SSI and their properties when configured for each mode.

ELECTRICAL SPECIFICATION

The ADRV9001 SSI can operate in the standard single-ended CMOS compatible mode, or LVDS compatible mode. Both CMOS SSI and LVDS
SSI share the IO pads of the ADRV9001.
LVDS modes.
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Table 24
Serialization Factor Per Data Maximum Data Lane Rate
Lane (MHz)
32 80
32 160
16/8/2 80-SDR/160-DDR
8 80
8 160
32 983.04
16 491.52
12 368.64
16 983.04
12 737.28
CSSI Data Symbols Transmit and
Figure 31 shows the four channels with their corresponding inputs and outputs in the CMOS and
lists the ADRV9001 SSI work modes and the maximum support I/Q
Maximum Clock Rate
(MHz)
80
80
80
80
80
491.52
491.52
368.64
491.52
368.64
Receive.
ADRV9001
Maximum
Sample Rate for
I/Q (MHz) Data Type
2.5 SDR
5 DDR
Not Applicable SDR/DDR
10 SDR
20 DDR
30.72 DDR
30.72 SDR
30.72 SDR
61.44 DDR
61.44 DDR
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