Power-Supply Configurations - Analog Devices ADRV9005 Reference Manual

Reference Manual
POWER-SUPPLY RECOMMENDATIONS
domain powers multiple power pins, current tends to be distributed over multiple pins, and this helps to minimize I x R voltage drops on the FB
components.
RF and Clock Synthesizer Supplies
The noise performance of the power domain used to power the RF blocks directly affects the overall transceiver phase noise. Power the power
domains using separate traces with extra isolation using a low DCR FB such as the Murata BLM18KG121TN1D or similar device.
The power-supply noise rejection on the synthesizer power input pins is very low. This means that any noise ripple on these pins affects
the synthesizer performance. The RF synthesizer requires more critical supply decoupling because any noise or variation in voltage during
operation is directly imposed on the RF channel. See
ADRV9001 evaluation card.
The synthesizers are more susceptible to low-frequency noise than other supplies because they have programmable loop filters. The loop filter
bandwidth directly affects the supply noise rejection on the synthesizers. For example, if the loop filter bandwidth is 50 kHz, then any noise on
the supply below 50 kHz is not filtered. The roll-off of the loop filter provides the noise rejection above 50 kHz.
For each power domain, an FB with high isolation at the frequency of operation is recommended to help isolate the pin from the supply source
for best performance. This is especially important when operating in TDD mode. Such high isolation FBs tend to also have high DC resistance.
This trade-off is acceptable for the synthesizer power inputs because their low-current draws result in relatively small voltage drops well within
the supply tolerance range.
For domains that consume higher amount of current, ensure that voltage drops on in-series FBs do not exceed power domain voltage toleran-
ces. PANASONIC EXC-ML20A390U 39OHM or MURATA, BLM15AX300SN1D or BLM18KG121TN1D with low DCR are good candidates for
such FBs.
For power domains, which do not consume higher amount of current and simultaneously require higher level of isolation, use ferrite beads with
higher DCR. Taiyo Yuden, BK1005LL470-T is an example of the recommended high DCR FB.

POWER-SUPPLY CONFIGURATIONS

From the power-supply implementation point of view, the ADRV9001 can work in multiple configurations. This section outlines them in detail.
It depends on the final application of the ADRV9001 in the end system that provides the freedom to implement different ways to power the IC.
The final solution depends on the following:
1. If the external 1.0 V power domain is used or not.
2. Type of application: FDD or TDD
a. For FDD, if DPD and/or transmitter tracking calibrations are used or not.
3. Number of active receiver inputs and transmitter outputs.
a. Note that in a scenario where Rx2/Tx2 are used and Rx1/Tx1 are not used (not recommended scenario from an optimal power savings
point of view), there must be power supply to VANA1_1P3 (C8).
4. LO scheme.
a. Internal LOs with internal PLL + VCO + LO_GEN powered by internal LDO.
b. External LOs with internal LO_GEN powered by:
1. Internal LDO
2. External LDO
Note that even in scenarios when external LOs are used, power up the VRFVCO1_1P0 (B9), VRFVC01_1P3 (A10), and
►
VRFSYN1_1P3 (E11). The RF PLL1 is used to generate test signals during the initialization calibration stage. Therefore, provide
power supply to these blocks. After performing initial calibrations, power down these blocks internally.
This section outlines how decisions based on these descriptions impact the final power-supply interconnectivity.
Figure 299 outlines the recommended power supply interconnectivity in scenarios using the external 1.0 V analog power domain. In such
modes, reconnect the number of power-supply input pins assigned to the 1.3 V analog power domain physically on the PCB to the new 1.0
V analog power domain. In cases where an external RF LO is used, save more power by physically disconnecting/grounding LO supplies
powering up the internal LO generation blocks.
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Figure 295 for an example of how the power-supply connections are made on the
ADRV9001
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