Analog Devices ADRV9001 User Manual
  1. Manuals
  2. Brands
  3. Analog Devices Manuals
  4. Motherboard
  5. ADRV9001
  6. User manual
Analog Devices ADRV9001 User Manual

Analog Devices ADRV9001 User Manual

Hide thumbs Also See for ADRV9001:
Table of Contents

Advertisement

Quick Links

Download this manual
ADRV9001 System Development User Guide for the RF Agile Transceiver Family

ADRV9001 SYSTEM DEVELOPMENT USER GUIDE OVERVIEW

The ADRV9001 is a family designator assigned to the system development user guide (ADRV9001 for ADRV9002, ADRV9003, and
ADRV9004).
The ADRV9001 system development user guide covers the:
ADRV9002 integrated dual RF transceiver
►
ADRV9003 integrated single RF transceiver (excludes digital predistortion (DPD))
►
ADRV9004 integrated dual RF transceiver (excludes DPD)
►
This user guide details the functionality across the entire family. Some family members do not include all the features or functions. For each
feature and function, refer to the individual product data sheet.
analog.com
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND
LEGAL TERMS AND CONDITIONS.
Reference Manual
ADRV9001
Rev. 0 | 1 of 351

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ADRV9001 and is the answer not in the manual?

Questions and answers

Related Manuals for Analog Devices ADRV9001

Summary of Contents for Analog Devices ADRV9001

  • Page 1: Adrv9001 System Development User Guide Overview

    ADRV9001 System Development User Guide for the RF Agile Transceiver Family ADRV9001 SYSTEM DEVELOPMENT USER GUIDE OVERVIEW The ADRV9001 is a family designator assigned to the system development user guide (ADRV9001 for ADRV9002, ADRV9003, and ADRV9004). The ADRV9001 system development user guide covers the: ADRV9002 integrated dual RF transceiver ►...

  • Page 2: Table Of Contents

    ADRV9001 in a Single-Band 2T2R FDD Enhanced Rx SSI Mode........71 Type Small-Cell Application......10 Power Saving for LSSI........71 ADRV9001 in a Dual-Band 2T2R FDD Type SSI Timing Parameters........72 Small-Cell Application........12 API Programming ..........72 ADRV9001 in a Single-Band 2T2R TDD CSSI/LSSI Testability and Debug.....74...
  • Page 3 Reference Manual ADRV9001 TABLE OF CONTENTS Frequency Hopping with Rx/ORx Gain ADRV9001 DPD Performance ...... 211 Control............126 Closed Loop Gain Control (CLGC)....212 Special Frequency Hopping Operations..127 DPD/CLGC Configuration ......213 Integration with Other Advanced Features..128 Board Configuration ........222 Frequency Hopping API Programming...128 Save and Load DPD Coefficients from Last Transmitter Signal Chain........
  • Page 4 Transmitter RF Port Impedance Match RF and Data Port Transmission Line Layout. 275 Measurement Data ........259 Isolation Techniques Used on the External LO Port Impedance Matching ADRV9001 Evaluation Card......282 Network............260 Power-Supply Recommendations..... 285 External LO Impedance Match Power Management Considerations....285 Measurement Data........263...

  • Page 5: How To Use This Document

    Reference Manual ADRV9001 HOW TO USE THIS DOCUMENT Figure 1. Flowchart for Document Navigation analog.com Rev. 0 | 5 of 351...

  • Page 6: Block Diagram

    Reference Manual ADRV9001 BLOCK DIAGRAM Figure 2. ADRV9002 Block Diagram analog.com Rev. 0 | 6 of 351...

  • Page 7: Product Highlights

    Reference Manual ADRV9001 PRODUCT HIGHLIGHTS ADRV9002 ADRV9002 delivers a versatile combination of high performance and low power consumption required by battery-powered radio equipment. It can operate in both the frequency division duplex (FDD) and time division duplex (TDD) modes. The ADRV9002 operates from 30 MHz to 6000 MHz, which covers the very high frequency (VHF), licensed and unlicensed cellular bands, and industrial, scientific, and medical (ISM) bands.
  • Page 8 Reference Manual ADRV9001 PRODUCT HIGHLIGHTS For sample rates above 2.5 MHz, single channel data is serialized over four lanes with two additional lanes required for a clock (SDR or DDR) and a frame synchronization signal, which supports a maximum sample rate of 20 MHz.

  • Page 9: Adrv9003

    Reference Manual ADRV9001 PRODUCT HIGHLIGHTS The ADC in the receive chain possesses a high dynamic range. Assuming 0 dB attenuation, the ADC’s noise and maximum input power referred to the RF input are -142 dBm/Hz and 8.6 dBm, respectively. These levels translate into a dynamic range in excess of 150 dB on a per Hertz basis.

  • Page 10: Adrv9001 Example Use Cases

    ADRV9001 EXAMPLE USE CASES The section provides an overall idea on how an ADRV9001 integrated transceiver can operate as an RF front end in different applications. The list is not exhaustive, and there are other applications the ADRV9001 can serve.
  • Page 11 LO Generation In FDD type small-cell applications, the ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation.

  • Page 12: Adrv9001 In A Dual-Band 2T2R Fdd Type Small-Cell Application

    Dual-Band 2T2R FDD Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete dual and RF-to-bits signal chain that can serve as RF front end in small-cell type applications. Note that in the proposed solution, only one band can be used at a time. The ADRV9001 dual receiver and transmitter signal chains enables users to implement multiple input multiple output (MIMO) or diversity in their system.
  • Page 13 LO Generation In FDD type small-cell applications, the ADRV9001 can use its internal LO to generate RF LO1 for uplink (Rx1 and Rx2) and RF LO2 for downlink (Tx1 and Tx2). It is also possible to use external LO inputs in this mode of operation. Note that only one set of the receiver inputs can be used at a time.

  • Page 14: Adrv9001 In A Single-Band 2T2R Tdd Type Small-Cell Application

    Constraints and Limitations LO Generation In TDD type small cell applications, the ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. It is also possible to use external LO inputs in this mode of operation.
  • Page 15 The DPD functionality can be used in the 2T2R TDD mode. The ADRV9001 can perform the DPD operation or observation receiver data can be sent to the baseband processor through the receiver data port during transmitting operation. The receiver path used during DPD operation to perform transmitter observation is also used by the transmitter tracking calibrations.

  • Page 16: Adrv9001 In 1T1R Fdd With Dpd Type Application

    Constraints and Limitations LO Generation In 1T1R FDD+DPD type applications, the ADRV9001 can use its internal LO to generate RF LO1 for uplink and RF LO2 for downlink. For applications with stringent RF LO requirements, the use external LO inputs.
  • Page 17 DGPIOs Digital GPIOs can be used to perform the real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs operating as inputs control the receiver gain, transmitter attenuation, AGC operation, and other elements of the ADRV9001 transceiver. Depending on the ADRV9001 operation, up to 4 GPIOs may be used by the data port interface.

  • Page 18: Adrv9001 In A Tetra Type Portable Radio Application

    The DPD functionality can be used in the 1T1R TDD mode. The DPD operation can be performed by the ADRV9001 or receiver data can be sent to the baseband processor through receiver data port during transmitter operation. The receiver path used during DPD operation to perform analog.com...
  • Page 19 DGPIOs Digital GPIOs can be used to perform the real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs operating as inputs control the receiver gain, transmitter attenuation, AGC operation, and other elements of the ADRV9001 transceiver. Depending on the ADRV9001 operation, up to 4 GPIOs may be used by the data port interface.

  • Page 20: Adrv9001 In A Dmr Type Portable Radio Application

    RF front end in DMR type applications. For systems that demand superior LO phase noise performance, the ADRV9001 allows users to apply external RF LO. The ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for the receiver signal chain.
  • Page 21 DGPIOs For DMR type applications, the ADRV9001 supports RF Monitor mode of operation. DGPIO pins are used to send wake-up signal to the baseband processor, and allow the baseband processor to move the ADRV9001 into Monitor mode using hardware pins (instead of API command).

  • Page 22: Adrv9001 In An Fdd Type Repeater Application

    LO Generation In the FDD type Repeater application, the ADRV9001 can use its internal LO to generate RF LO1 for uplink (example, Tx1, and Rx2) and RF LO2 for downlink (example, Tx2, and Rx1). It is also possible to use external LO inputs in this mode of operation.
  • Page 23 DGPIOs Digital GPIOs can be used to perform real-time monitoring of states of internal ADRV9001 blocks. Digital GPIOs operating as inputs control the receiver gain, transmitter attenuation, AGC operation, and other elements of the ADRV9001 transceiver. Depending on the ADRV9001 operation, up to 4 GPIOs may be used by the data port interface.

  • Page 24: Adrv9001 In An Fdd Type Repeater Application Using Internal Loopbacks

    LO Generation In the FDD type repeater application, the ADRV9001 can use its internal LO to generate RF LO1 for uplink (example, Tx1, and Rx2) and RF LO2 for downlink (example, Tx2, and Rx1). It is also possible to use external LO inputs in this mode of operation.
  • Page 25 RF Front End For LO generation, the ADRV9001 uses internal VCO that generates square wave type signal. A square wave LO produces harmonics. For example, depending on RF matching used on the RF ports, the second LO harmonic can be as high as −50 dBc, and the third harmonic can be as high as −9 dBc.

  • Page 26: Adrv9001 In A Tdd Type Repeater Application

    TDD Type Repeater Overview With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end in TDD type repeater or frequency translator applications. In TDD type applications, internal DPD block can be used to linearize external power amplifier and improve overall system efficiency.
  • Page 27 Constraints and Limitations LO Generation In the TDD type repeater application, the ADRV9001 can use its internal LO to generate RF LO1 for both uplink and downlink. It is also possible to use external LO inputs in this mode of operation.

  • Page 28: Adrv9001 In A Radar Type Application

    With a minimum number of external components, the ADRV9001 transceiver can be used to build a complete RF-to-bits signal chain that can serve as RF front end building block in Radar type applications. The ADRV9001 internal AGC can be used to autonomously monitor and set the appropriate gain level for the receiver signal chains.
  • Page 29 The DPD functionality can be used in the 2T2R TDD mode. The DPD operation can be performed by the ADRV9001 or ORx data can be sent to the baseband processor through the receiver data port during transmitter operation. The receiver path used during DPD operation to perform the transmitter observation is also used by the transmitter tracking calibrations.

  • Page 30: Software System Architecture Description

    The ADRV9001_API.chm is in compressed HTML format. For security reasons, open the .chm files only from a local drive. If there is an ► attempt to open from a network drive, the file may look empty. The ADRV9001 is a baseline device for the product family; therefore, all API and evaluation systems use this product number to describe the ► product.

  • Page 31: Folder Structure

    15, the developer can organize the ADRV9001 API into a custom folder organization, if required. This operation, however, does not permit the developer to modify the content of the ADRV9001 API source code, except for the hardware abstraction layer (HAL) placeholder files, which are detailed later in this chapter and in Figure Figure 15.

  • Page 32: Customizing The System Architecture And File Structure

    /c_src/devices: The device folder includes the main API code for the ADRV9001 transceiver as well as the auxiliary devices the APIs used for the demo of the ADRV9001. The /ADRV9001 folder contains the high-level function prototypes, data types, macros, and source code used to build the final software system.
  • Page 33 The adi_platform.c file is where the HAL is chosen. For the default HAL provided by Analog Devices, it is also implemented in the adi_platform.c file. However, make no edits to the default HAL stored under linux_uio\. Users have placeholder files in the customer\ folder.
  • Page 34 Reference Manual ADRV9001 SOFTWARE SYSTEM ARCHITECTURE DESCRIPTION Figure 17. API Folder Structure with Customer Interaction Points Highlighted More details are provided in the customer\ folder in the Software Integration chapter, which goes into more specifics on the HAL. At this point...

  • Page 35: Software Integration

    The users who develop code to target custom hardware platforms use different drivers for the peripherals, such as the SPI and GPIO, compared to the drivers chosen for the ADI evaluation platform. The HAL interface is a set of function pointers that the ADRV9001 API uses to access the target platform hardware.
  • Page 36 Once done, the adi_platform.c code automatically switches to use of the placeholder customer code under the customer\ folder. Following is a code snippet from adi_adrv9001_hal_customer.c, located under customer\adrv9001\. It shows each function required by the HAL to support a customer-specific platform. Read the example HAL implementation provided under the linux_uio\ folder to understand the purpose of each function, as well as the acceptable return values.
  • Page 37 The issue arises due to a discrepancy between the “standard” bit field control of SPI settings (clock polarity (CPOL), clock phase (CPHA), etc.) and the approach Analog Devices takes with SPI control of the devices. Where most devices use normal Binary encodings for their SPI control (00, 01, 10, 11), Analog Devices uses Gray Code for SPI control (00, 01, 11, 10).
  • Page 38 Next are the customer_adi_adrv9001_hal_spi_write(…) and customer_adi_adrv9001_hal_spi_read(…) functions. In accordance with the workings of the bcm2835 library, these functions write data to the ADRV9001 after driving the chip-enable line low. For the custom- er_adi_adrv9001_hal_spi_read(…) function, data is also accepted from the device on the DO line (MISO on the Raspberry Pi).
  • Page 39 Reference Manual ADRV9001 SOFTWARE INTEGRATION delay(1); bcm2835_spi_begin(); bcm2835_spi_transfern(txData, numTxBytes); bcm2835_spi_end(); delay(1); bcm2835_gpio_write(CE_PIN, HIGH); return 0; int32_t customer_adi_adrv9001_hal_spi_read(void *devHalCfg, const uint8_t txData[], uint8_t rxData[], uint32_t numTxRxBytes) /* Customer code goes here */ bcm2835_gpio_write(CE_PIN, LOW); delay(1); bcm2835_spi_begin(); bcm2835_spi_transfernb(txData, rxData, numTxRxBytes); bcm2835_spi_end(); delay(1);...

  • Page 40: Developing The Application

    The devHalInfo is passed to the platform specific HAL function as a void *devHalCfg. The ADRV9001 API functions do not read or write the devHalInfo but pass it as a parameter to all HAL function calls.
  • Page 41 ADRV9001 device is targeted (SPI chip select) when a particular ADRV9001 API function is called. The developer may need to store other hardware information unique to a particular ADRV9001 device in this structure such as timer instances or log file information.

  • Page 42: System Initialization And Shutdown

    TES CONFIGURATION AND INITIALIZATION The TES provides a Config tab that contains all the setup options for the ADRV9001. Under the Config tab, configure each channel of the device for a required profile under the Device Configuration subtab, which sets high level parameters such as duplex mode, data port sample rates, and RF channel bandwidth.

  • Page 43: Api Initialization Sequence

    API functions briefly. For details of each API function, refer to the Doxygen document. Note for MIMO systems with multiple input and output channels, multiple ADRV9001 devices might be involved. To synchronize among all the devices, it requires a common device clock (DEV_CLOCK) and an MCS signal so that all the internally generated analog and digital clocks are aligned among all the devices.
  • Page 44 Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN Resource Loading After analog initialization, a set of APIs is used to load required resources such as stream image, ARM image, programmable FIR (PFIR) coefficients, and so on. It also enables the internal microprocessor and initializes the digital clocks.

  • Page 45: State Change Timing

    SYSTEM DEBUGGING The "System Debugging" feature runs a system check on the ADRV9001 to ensure that all main functionalities of the device are working correctly. The system check is primarily a debugging tool to assist in narrowing down any issues with the system. It can also be run at each start-up to check if the device booted correctly.
  • Page 46 Reference Manual ADRV9001 SYSTEM INITIALIZATION AND SHUTDOWN *** ADRV9001 Pre-Calibrate System Debugging Started *** --> . Hardware Reset --> . API Version OK - API Version = 67.3.2 --> . Configure SPI --> . Check SPI --> . Check Power Supplies -->...

  • Page 47: Warm Boot

    Therefore, skip the time-consuming initial calibration procedure during device initialization stage for a much shorter boot-up time. To achieve this, the ADRV9001 device provides user APIs to save the initial calibration coefficients after performing the first initial calibration (cold boot) and then loads the saved initial calibration coefficients to the device before the subsequent boot-ups (warm boot).

  • Page 48: Boot-Up Timing

    BOOT-UP TIMING Many users have a vested interest in knowing the time needed for the ADRV9001 devices to perform certain tasks, such as Init Calibrations, ARM image loading, profile configuration, etc. It is also common that the RF Bring-Up time (time from HW RESET to RF Enabled) must be within a limit for certain applications.
  • Page 49 Irrespective of the application, the methodology remains the same. The idea is to generate code that programs the setup to use with the ADRV9001 product, modify it to include functionality unique to an application, if necessary, and then time its execution. There are several aspects to consider with this idea, the foremost being the choice of programming language.
  • Page 50 Example Results During experiments, Analog Devices focused on characterizing the time taken for the device to boot-up from RESET to RF ENABLED using a given digital mobile radio (DMR) configuration (note: this configuration is just an example use case. It does not represent a “best case”...
  • Page 51 (such as the ARM image) and running the initial calibrations. Loading values to the memory can improve with a faster SPI implementation. Also note that the SPI implementation on the Analog Devices platform is not necessarily optimized for speed.

  • Page 52: Serial-Peripheral Interface (Spi)

    100 pF load at 20 MHz Note: Any value not listed in the table is invalid. For more details, refer to the ADRV9001_API Doxygen file provided in the ADRV9001 SDK package. SPI BUS SIGNALS The SPI bus consists of the following signals: Serial clock (SCLK) ►...

  • Page 53: Spi Data Transfer Protocol

    Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Serial Clock (SCLK) SCLK is the serial interface reference clock driven by the baseband processor (uses the SPI_CLK pin). It is only active while CSB is low. The maximum SCLK frequency is 45.45 MHz.
  • Page 54 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Single-Byte Data Transfer When enSpiStreaming = 0, choose a single-byte data transfer. In this mode, CSB goes active-low, the SCLK signal activates, and the address is transferred from the baseband processor to the device.

  • Page 55: Timing Diagrams

    Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Example: MSB-First Multibyte Transfer, Autodecrementing Address To complete a 4-byte write starting at register address 0x02A and ending with register 0x027 in MSB-first format, follow these instructions when programming the controller: Make sure that fourWireMode = 1 - the device is configured to work with the 4-wire interface.

  • Page 56: Spi Test

    ► Toggle the reset pin to reset the ADRV9001 ► Write register 0x0 with value 0x3C to set the ADRV9001 SPI to the 4-wire mode, or with value 0x24 to set the ADRV9001 SPI to the 3-wire ► mode. Write any value to scratch register 0x009, then read register 0x009 to validate if the read value is the same as the write value.
  • Page 57 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Table 19. SPI Main Pin Mapping (Continued) MCS0 MCS1 MCS2 MCS3 MCLK MISO MOSI GPIO8 ✓ GPIO9 ✓ GPIO10 ✓ GPIO11 ✓ While multiple pin options exist when assigning a chip-select pin, only a single SPI sub device can be used at a time. Currently, MCS0 can be assigned to any available GPIO pin.
  • Page 58 Reference Manual ADRV9001 SERIAL-PERIPHERAL INTERFACE (SPI) Table 20. SPI Main Configure Struct Definition (Continued) Type Name Description uint8_t spiData[SPI_MASTER_TOTAL_BYTES_MAX] Bytes to be written to the SPI sub device. By default populated with zeros. Note: SPI Main makes no distinc- tion between op-codes, addresses, and data; these are all treated as one in the spiData array.

  • Page 59: Data Interface

    One-lane data mode, I/Q data, or other format data are serialized onto one single lane. ► Four lanes data mode, which is valid only when the ADRV9001 transmits or receives I/Q samples, and the I/Q samples are 16 bits wide. In ►...
  • Page 60 LVDS SSI electrical specifications. It is recommended to closely match the trace lengths of SSI clock, strobe, data signals into each transmit or receive channel. The ADRV9001 SSI has configurable delay cells on the LVDS/CMOS input and output circuits, which allow small adjustments to the phase relationship between the strobe/data and clock.

  • Page 61: Cmos Synchronous-Serial Interface (Cmos-Ssi)

    Reference Manual ADRV9001 DATA INTERFACE Table 22. CSSI Electrical Specification (Continued) Symbol Parameter Units Output-voltage low 0.45 Clock frequency at 80 MHz Load capacitance supported for an 80 MHz clock waveform Table 23. LSSI Electrical Specification Symbol Parameter Conditions Units...
  • Page 62 For I data duration and low for Q data duration. For a 16-bit data sample, TX_STROBE is high for 16 clock cycles (I data sample) and low for ► 16 clock cycles (Q data sample). CSSI Data Symbols Transmit and Receive The previous sections describe data transfer with I/Q format with 16-bit width. When the ADRV9001 internal modulation/demodulation is enabled (see the Transmitter Signal Chain Receiver Demodulator sections), the data transfer between the ADRV9001 and baseband processor is 2 bits or 16 bits I only data (denoted as symbol to differentiate with I/Q complex samples).
  • Page 63 Reference Manual ADRV9001 DATA INTERFACE Figure 33. Receive CSSI Timing for 2-Bit Symbols (MSB First) Figure 34 shows the transmit CSSI (Tx) for 2-bit data symbols. Figure 34. Transmit CSSI Timing for 2-Bit Symbols (MSB First) Figure 35 shows the receive CSSI (Rx) for 8-bit data symbols.
  • Page 64 Figure 38. Transmit CSSI Timing for 16-Bit Symbols (MSB First) Receive CSSI with Two, Four, and Eight Times Data Clock Rates The ADRV9001 receive CSSI supports two, four, or eight times of the data clock rate for some applications. Figure...
  • Page 65 Reference Manual ADRV9001 DATA INTERFACE Figure 41. Receive CSSI Timing with 8 Times Data Clock Rate for 16-Bit I/Q Data Sample (MSB First), 224 Cycles Figure Figure 43, and Figure 44 show the receive CSSI (Rx1 and Rx2) in the frequency deviation mode with 16-bit data symbol with two, four, and eight times clock rates.
  • Page 66 Reference Manual ADRV9001 DATA INTERFACE RX_QDATA3_OUT: output serial data stream of Q sample high byte. ► Figure 45 shows the receive CSSI (Rx1 and Rx2) for a four-lane format with MSB first configuration. Figure 45. Four-Lane Mode Receive CSSI Timing for 16-Bit I/Q Data Sample (MSB First) The four-lane mode CSSI transmits the interface of each channel (Tx1 and Tx2).
  • Page 67 Figure 47. Receive CSSI DDR Clock Relation with Strobe/Data Figure 48 shows the transmit CMOS SSI with DDR clock in relation to the strobe/data, with respect to the ADRV9001. Each edge of the clock (positive and negative) samples the corresponding strobe/data sample based on the interface setup/hold timing.

  • Page 68: Lvds Synchronous-Serial Interface (Lvds-Ssi)

    Reference Manual ADRV9001 DATA INTERFACE Figure 50. Four-Lane Mode Transmit CSSI DDR Timing for 16-Bit I/Q Data Sample LVDS SYNCHRONOUS-SERIAL INTERFACE (LVDS-SSI) Receive LSSI The LSSI receive interface of each channel (Rx1 and Rx2) is an 8-wire LVDS interface consisting of: RX_DCLK_OUT (±): differential output clock.
  • Page 69 Reference Manual ADRV9001 DATA INTERFACE Figure 52. Receive LSSI Timing for 12-Bit I/Q Data Sample over Two Lanes (MSB First) The RX_STROBE signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high: For a half-clock cycle at the start of I and Q sample transmit.
  • Page 70 Reference Manual ADRV9001 DATA INTERFACE An optional LVDS port (alternative function of Digital GPIO) can also be configured as an output LVDS pad used as a reference clock TX_DCLK_OUT (±) for the baseband processor. Use TX_DCLK_OUT to generate the LSSI clock, strobe, and data signal.

  • Page 71: Enhanced Rx Ssi Mode

    Receive LSSI with Two, Four, and Eight Times Data Clock Rates The ADRV9001 receive LSSI supports the two, four, or eight times of the data clock rate for some applications, which is similar with the receiver CSSI mode (see the timing diagrams in the Receive CSSI with Two, Four, and Eight Times Data Clock Rates section).

  • Page 72: Ssi Timing Parameters

    Tx t (Minimum) 390 ps Strobe/data hold after clock HOLD API PROGRAMMING The ADRV9001 SSI configuration is performed in the chip initialization stage and based on the following data structure. typedef struct adi_adrv9001_SsiConfig adi_adrv9001_SsiType_e ssiType; adi_adrv9001_SsiDataFormat_e ssiDataFormatSel; adi_adrv9001_SsiNumLane_e numLaneSel; adi_adrv9001_SsiStrobeType_e strobeType;...
  • Page 73 Reference Manual ADRV9001 DATA INTERFACE adi_adrv9001_SsiTxRefClockPin_e txRefClockPin; bool lvdsIBitInversion; bool lvdsQBitInversion; bool lvdsStrobeBitInversion; uint8_t lvdsUseLsbIn12bitMode; bool lvdsRxClkInversionEn; bool cmosDdrPosClkEn; bool cmosClkInversionEn; bool DdrEn; bool rxMaskStrobeEn; } adi_adrv9001_SsiConfig_t; In the data structure, the previously mentioned SSI modes are defined for each Tx/Rx channel.

  • Page 74: Cssi/Lssi Testability And Debug

    Sets the power-down mode for the specified channel and SSI type. CSSI/LSSI TESTABILITY AND DEBUG The ADRV9001 SSI has built-in test pattern generator and checker to quickly test and debug the SSI between the ADRV9001 and baseband processor. Figure 63 shows the ADRV9001 SSI testability and debug diagram with a baseband processor.
  • Page 75 (PRBS) (LSSI only) pattern and send it to the baseband processor. Enable the receive debug function by calling adi_adrv9001_Ssi_Rx_Test- Mode_Configure(). Check the specified test pattern at the SSI output to test if the receive SSI from the ADRV9001 to BBIC functions correctly.
  • Page 76 When the transmit and receive SSI run at the same clock rate, use the pattern generator and checker to verify the functionality of the whole system SSI. Note that both the ADRV9001 TX and RX radio state must be in the “RF_ENABLED” state to ensure the TX/RX SSI is enabled when setting the SSI loopback test function.

  • Page 77: Microprocessor And System Control

    So, it is necessary to use a stream image for each configuration of the device. In this way, when the user saves configuration files (.c) using the ADRV9001 TES, a stream image is also saved automatically. This stream file is then used when using these configuration files.

  • Page 78: System Control

    Tx2 datapath For ADRV9001 to receive and react to control signals, move it to the primed state. The primed state indicates that the system is ready for operation when the transmit and receive channels are enabled. After the channel is primed, and to start transmit or reception activities, further...
  • Page 79 Figure 65. Visualization of Timing Parameters Broadly, the delays in the system are described as follows: Enable Setup Delay is the time taken for the ADRV9001 to power up its analog front end (AFE). This may or may not include PLL tuning ►...
  • Page 80 Transmit Timing Definition Transmit timing parameters define the events in order from the start of transmission at the ADRV9001 data port to the end when the transmit burst is sent through the antenna to the air.
  • Page 81 66. This saves power by reducing unnecessary AFE on time. For example, if the propagation delay is 2.5 ms, whereas the enableSetupDelay provided by the ADRV9001 is 8 μs, an AFE can be off to avoid burning power for the first 2.492 ms of the propagation time.
  • Page 82 ADRV9001 further controls receive analog components, receive interface, and the external LNA (if it is controlled by the ADRV9001 instead of the user) to make sure the received burst is sent to BBIC at the deterministic time as desired.
  • Page 83 Design Strategy for Receive Timing Parameters As described, the ADRV9001 provides the enableSetupDelay, which is the time required to power up the receiver front end. By knowing this, set the RX_ENABLE pin high as at least enableRiseToOnDelay in advance, as shown in Figure 68.
  • Page 84 (Note that enableFallToOffDelay is forced to 0 currently by the ADRV9001.). This time should not be larger than the guard time before the next frame. The longer this value is, a delay in the next Rx_enable rising edge can occur.
  • Page 85 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL – t if t is greater than t . For t is less than t , TX_ENABLE rising edge can happen TxEnaRise2On RxEnaFall2Off TxEnaRise2On RxEnaFall2Off TxEnaRise2On − t before TX_ENABLE falling edge. Figure 70 describes both cases.
  • Page 86 Timing Parameters with Power Savings Modes The ADRV9001 offers several channel power savings modes (Power Saving Mode 0, 1, and 2) that trade off better power savings with longer transition time to turn on and turn off a transmit or receive channel. For more details about power saving modes, see the...
  • Page 87 All the previously-mentioned descriptions are for internal LO scenarios. If the ADRV9001 is configured with the external LO mode, take the responsibility to configure or retune the external PLLs. The ADRV9001 channel power-up and power-down sequence in different power saving...
  • Page 88 } adi_adrv9001_ChannelEnablementDelays_t Note that the ADRV9001 reserves guardDelay for future use and forces it to 0 for both transmit and receive channels. In addition, for the transmit channel, reserve holdDelay for future use and force it to 0. For the receive channel, reserve fallToOffDelay for future use and force it to 0.
  • Page 89 Reference Manual ADRV9001 MICROPROCESSOR AND SYSTEM CONTROL Figure 77. ADRV9001 Provided Timing Parameters and the System Clock for the Selected Profile in TES Based on the information provided in Figure 77, further configure the ADRV9001 required timing parameters. Default Timing Parameters for Transmit Channels...
  • Page 90 When the ADRV9001 calculates the default values, it uses the transmit/receive propagation delay internally characterized for different profiles. Measure the propagation delay for the entire system to determine all the required timing parameters accurately. This includes a power amplifier, LNA, filters, and anything else that might be between the chip and antenna.
  • Page 91 As previously mentioned, the enableSetupDelay (EnaSetup) is the time taken for the ADRV9001 to power up its AFE, and the ADRV9001 also takes less time to finish the operations to power down its AFE at the falling edge of the transmitter/receiver enable signals.

  • Page 92: Api Execution Timing

    API EXECUTION TIMING The ADRV9001 APIs have several categories in how they interact between the BBIC and the ADRV9001. Most APIs communicate with the ADRV9001 through the mailbox, where the ADRV9001 ARM processor schedules tasks. These mailbox type APIs are usually not time critical and can take tens of microseconds up to several milliseconds, depending on the real-time operating system (RTOS) task status.

  • Page 93: Clock Generation

    CLOCK GENERATION In the ADRV9001, the CLKGEN generates all clocks for the converters and main digital. CLKGEN receives from two clocks, a high performance (HP) clock PLL and low power (LP) clock PLL. The high performance clock PLL has a programmable frequency range of 7.2 GHz to 8.8 GHz.

  • Page 94: Arbitrary Sample Rate

    ARBITRARY SAMPLE RATE With a programmable frequency range of both HP CLK PLL and LP CLK PLL (as mentioned previously), the ADRV9001 supports the arbitrary sample rate (ASR) mode, which provides great flexibility to configure the desired sample rates in the applications. The ASR mode supports an almost continuous range of rates up to 61.44 MHz, with a list of dead zones mainly due to the limitations in the decimation/interpolation rate...
  • Page 95 Due to the complexity of the datapath, there is no freedom to select own CLK PLL clock frequencies and datapath configurations. Provide the desired sample rate only, and the ADRV9001 TES determines the appropriate ADRV9001 profile. Note: The above table provides a theoretical guideline of the dead zones. Double check the validity of the sample rates using the TES.

  • Page 96: Multichip Synchronization

    For example, in MIMO applications, MCS is the solution to align the data in time for multiple channels. Some applications not only require the delay to be deterministic but also require the phase to be the same. The ADRV9001 supports PLL phase synchronization in addition to the deterministic delay.
  • Page 97 Note: If choosing the MCSMODE_ENABLED mode, which does not guarantee phase synchronization, the process is done only once after the device is initialized and at the calibrated state for the first time. This means after all MCS pulses are sent, and all ADRV9001 components are synchronized, no more pulses are needed.
  • Page 98 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION To select one of the modes, use this structure: typedef enum adi_adrv9001_McsMode { ADI_ADRV9001_MCSMODE_DISABLED = 0, /*!< Multi Chip Synchronization disabled */ ADI_ADRV9001_MCSMODE_ENABLED, /*!< Multi Chip Synchronization enabled */ ADI_ADRV9001_MCSMODE_ENABLED_WITH_RFPLL_PHASE /*!< Multi Chip Synchronization enabled with RFPLL phase } adi_adrv9001_McsMode_e;...

  • Page 99: Mcs Substates (Internal Mcs State Transition)

    MCS procedure. The first API verifies the synchronization status of the analog and digital subsystems of the device after issuing one or all of the MCS pulses. The second API verifies the current state of adrv9001 software after issuing one or all of the MCS pulses.

  • Page 100: Sample Delay And Read Delay

    They are reset to false after the fourth pulse. The states after the fourth pulse reflect the correct expected states. 4: MCS done After all six pulses are received, MCS is finished. At this point, ADRV9001 is in the MCS Done substate. Start to prime the channels to prepare for normal operations.
  • Page 101 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION Read Delay: It helps delay FIFO read time. Once information is fed in the FIFO, this value guarantees the FIFO has samples for all channels before reading. Figure 89. Tx MCS to Strobe Timing Diagram Figure 90.

  • Page 102: Phase Synchronization

    Analog Devices also allows an adjustment to use the above method. Fundamentally, this is controlled from the baseband processor, and there is full control over how data is timed. In contrast, on the transmitter side, the ADRV9001 does not control how the data is passed in.
  • Page 103 Reference Manual ADRV9001 MULTICHIP SYNCHRONIZATION Figure 92. Phase Error After Synchronization Between Two LOs analog.com Rev. 0 | 103 of 351...

  • Page 104: Synthesizer Configuration And Lo Operation

    SYNTHESIZER CONFIGURATION AND LO OPERATION The ADRV9001 family devices employ four PLL synthesizers: clock, RF (×2), and auxiliary. Each PLL is based on a fractional-N architecture and consists of a common block made up of a reference clock divider, phase frequency detector, charge pump, loop filter, feedback divider, digital control block, and either a 1 or 4 core voltage-controlled oscillator (VCO).

  • Page 105: Auxiliary Synthesizer

    High power means low LO phase noise, and vice versa. The ADRV9001 provides two modes of retuning the PLL: the normal mode and fast mode. In terms of phase noise performance, there is no difference between the fast and normal modes. However, the normal mode tracks temperature over time while the fast mode does not.

  • Page 106: Rf Pll Loop Filter Recommendations

    Single-Ended vs. Differential External LO Note that the ADRV9001 evaluation board only supports differential external LO. However, there is no restriction to use single-ended LO in the end system. Change clocks.ext1LoType and clocks.ext2LoType from 0 to 1. The following Enum contains this.

  • Page 107: Api Operation

    API OPERATION Data Structure and Enumerations Table 43. Data Structures Related to LO Operation Data Structure Description adi_adrv9001_Device_t Data structure to hold ADRV9001 device instance settings. adi_adrv9001_Carrier_t Carrier structure for carrier configuration. adi_common_Port_e Enumeration of port types. adi_common_ChannelNumber_e Enumeration of channel numbers.
  • Page 108 Change the PLL BW into the ADRV9001 chip initialization state based on the specified DEV_CLK_IN frequency and LO phase noise requirements. The ADRV9001 TES has the RF PLL loop filter bandwidth configuration interface to tune and achieve the best phase noise in the system.

  • Page 109: Frequency Hopping

    Therefore, it is possible to hop two pairs of channels (Rx1/Tx1 and Rx2/Tx2) separately by using two different PLLs. KEY SIGNALS To understand FH operations in the ADRV9001, it is crucial to first understand several key signals the BBIC needs to set up such as “HOP”, “Tx Setup”, and “Rx Setup” signals.

  • Page 110: Modes Of Operation

    With the Tx_Setup and Rx _Setup signals, as shown in Figure 102, Rx and Tx frames alternate. MODES OF OPERATION The ADRV9001 provides four FH modes to achieve various framing requirements, as shown in Table Table 45. Frequency Hopping Modes of Operation Total Frame Duration...
  • Page 111 Fundamentally, the ADRV9001 defines two modes of PLL usage: PLL Mux and PLL Retune. The PLL Mux mode utilizes two PLLs. While one PLL is in operation, the other one is tuning. The two PLLs are swapped during the transition time. This mode is suitable for use cases where the transition time is not sufficiently long to complete channel setup and PLL tuning.

  • Page 112: Frequency Hopping Table

    The ADRV9001 supports the loading of two tables (table A and B), each with a minimum length of 1, and a maximum length of 64 entries (a total of 128 hop entries/frequencies, if two tables are used).
  • Page 113 Automatic Increment The standard mode of operation in the ADRV9001 is the automatic increment mode. In this mode, FH begins at index 0, and continues to iterate over the table until the number of table entries is reached. Once reached, it wraps back to index 0. This is also called the “Loop” mode when one hopping table is used.
  • Page 114 At initialization, assign up to 6 DPGIO pins to provide 64 possible indices to the current hopping table. During operation, set the DGPIO pins prior to the upcoming hop edge. At each hop edge, the ADRV9001 samples the DGPIO pins to understand the hopping table entry to use.
  • Page 115 Frequency Hopping Table Real-Time Process Pre-process refers to the hopping tables being sent to the ADRV9001 and processed before the FH operation begins. In such a case, user should fully know the hopping table content at the initialization and it cannot be changed on the fly.
  • Page 116 Therefore, the ADRV9A001 does not read from table B yet at this point. It reads from table B at the upcoming hop signal edge (the first falling edge). At the first falling edge of the hop signal, the ADRV9001 reads the new entry from table B and switches to table A. This hop frame (from the ►...

  • Page 117: Selecting The Channel And Profile

    Ensure the Hop Table Select Pin is set before the appropriate hop edge. ► Use the Hop Table Select table pin to force the switch to the second table at any time. The ADRV9001 does not require the switch to happen ►...
  • Page 118 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 111. Frequency Hopping Minimum Timing Table 48. Frequency Hopping Timing Parameters Minimum Timing Timing Parameter Description Time (µs at 184.32 MHz) Time required by the internal controller to prepare the next transmitter frame. Min: 13 µs NextTxFramePrepare Time required by the internal controller to prepare the next receiver frame.
  • Page 119 PLL retuning time. propagationDelay Delay from ADRV9001 digital This time is not used for any delays in the ADRV9001. Enable interface to antenna. the interface and begin data transmission ample time prior to the end of the transition time to account for the propagation delay.
  • Page 120 Delay from antenna to the Rx This parameter is profile and board layout dependent. interface. Not necessary to configure the ADRV9001, but can be necessary to derive the other timing parameters enableRiseToOnDelay Delay between the hop edge and Min: enableRiseToOnDelay + ena- LNA power-up.
  • Page 121 Figure 115. Frequency Hopping Typical TRx Timing for PLL Mux Mode For the TRx operation, because a hop edge can mark both the start and end of an receiver or transmitter frame, the ADRV9001 guarantees that the receiver and transmitter front ends are not powered up at the same time.

  • Page 122: Additional Frequency Hopping Operations

    The delay parameter specifies the delay in terms of hop frames after the first transmitter setup rising edge is received. By design, the ADRV9001 enforces a minimum delay for both the transmitter and receiver of 1 in the PLL Mux mode. However, for transmitter only, this delay can be greater than 1.
  • Page 123 Reference Manual ADRV9001 FREQUENCY HOPPING continuously toggled. After the pulse train of transmitter setup stops (meaning a hop edge without a preceding transmitter setup rising edge), the transmitter channel is powered down at the next hop edge. A subsequent transmitter setup begins the process again.
  • Page 124 Reference Manual ADRV9001 FREQUENCY HOPPING Figure 120. Tx Only with Long Propagation Delay for PLL Retune Mode Transmitter Only with Short Propagation Delay There is a restriction to how long before the hop edge the transmitter setup falling edge must come. For profiles with very short propagation delays, this means the interface is on longer than required for valid data to reach the analog front end.
  • Page 125 ORx Operation The ADRV9001 supports ORx operation in the FH modes. ORx in FH works like the normal TDD mode. During the actual Tx frame, set the ORx enable signal (assign to a DGPIO pin) high to enable ORx. Before the end of the Tx frame, set ORx low to disable ORx. Note this is required regardless of whether the next frame is Tx or Rx.

  • Page 126: Diversity Mode

    In FH, if the AGC is configured and the resetOnRxOn field is true, then the starting Rx gain for each frame is taken from the hopping table instead of the resetOnRxonGainIndex field in the AGC configuration. With manual gain control, the ADRV9001 programs the manual gain index for each frame based on the gain information in the hopping table or through the DGPIOs.

  • Page 127: Special Frequency Hopping Operations

    FREQUENCY HOPPING The ADRV9001 allows up to 3 DGPIO pins to select the Rx gain or Tx attenuation for each hopping frame from a Rx gain or Tx attenuation table with a maximum of eight entries. The GPIO pins formulate an index to the defined Rx gain or Tx attenuation table and the GPIO pins are sampled at the hop edge.

  • Page 128: Integration With Other Advanced Features

    Frequency Hopping with DPD Frequency Regions The ADRV9001 supports FH to work with digital predistortion (DPD). The ADRV9001 divides frequencies into 8 frequency regions. Specify the start and end frequencies of 7 regions. There is one last region (8 region) to “catch all”, which captures the remaining range of the frequencies.
  • Page 129 Note: The preceding table shows that the API adi_adrv9001_fh_HopTable_Dynamic_Configure() is only used to dynamically load the hopping table in the ADRV9001 evaluation system due to the limitation of the FPGA. In the user systems adi_adrv9001_fh_HopTable_Stat- ic_Configure() is the correct API to load the hopping table either statically at the initialization time or dynamically during hopping. To learn the API use in the different modes of FH operations, use the TES “Driver Debugger”...

  • Page 130: Transmitter Signal Chain

    (LSSI) mode. As mentioned earlier, the ADRV9001 supports many NB and WB standards. Depending on the selected standard and the specific symbol rate chosen through the API profile, the interface clock rate can vary significantly. Note that CSSI is a slow-speed interface and cannot cover this entire frequency range.

  • Page 131: Digital Front End (Dfe)

    Transmit Gain Table The transmitter attenuation block controls the transmitter output power. A transmitter gain table with 960 entries is loaded into the ADRV9001’s memory during initialization. Currently, only the first 840 entries are used. Each entry equals a 0.05 dB gain step. Therefore, there is a total gain range of 42 dB.
  • Page 132 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN Table 57. Sample Rows from the Tx Gain Table (Continued) Transmitter Total Transmitter Analog Attenuation Analog Attenuation Digital Attenuation Digital Attenuation Digital Attenuation Attenuation Index Attenuation (dB) Control Word[5:0] (dB) (dB) (Linear) Control Word[11:0] 0.15...
  • Page 133 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_CLGC = 4, } adi_adrv9001_TxAttenuationControlMode_e The following subsections discuss the first three modes. For the CLGC mode, see the Closed Loop Gain Control (CLGC) section. Bypass Mode Select the bypass mode when the transmitter attenuation mode is set as “ADI_ADRV9001_TX_ATTENUATION_CONTROL_MODE_BY- PASS”.
  • Page 134 Reference Manual ADRV9001 TRANSMITTER SIGNAL CHAIN GPIO Mode The general purpose input/output (GPIO) mode is another method to control the transmitter attenuation block. In this mode, two GPIO pins are used to increment or decrement the current attenuation value. An API command “adi_adrv9001_Tx_Attenuation_PinControl_Configure()”...
  • Page 135 Digital Predistortion (DPD) DPD is an optional feature available on the ADRV9001 device to achieve higher power amplifier efficiency, while still meeting the error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) requirements in the transmitter signal chain in compliance with standard requirements.

  • Page 136: Analog Front End (Afe)

    Digital-to-Analog Converter (DAC) The ADRV9001 integrates a 16-bit DAC, which can be operated at a standard rate of 184.32 MHz, 368.64MHz, or 552.96 MHz (note: with an arbitrary sample rate, DAC can operate at other different rates as well.) The selected profile sets the sampling rate. The DAC is auto-tuned to remove mismatches in the DAC units, which improves the linearity of the DAC.

  • Page 137: Transmit Data Chain Api Programming

    TRANSMIT DATA CHAIN API PROGRAMMING There are a set of transmitter data chain APIs for interaction with the ADRV9001 device transmit datapath. Some of them are discussed in the previous sections. The following table summarizes the list of available API functions with a brief description for each. For more up-to-date information and detailed descriptions, refer to the API Doxygen document.

  • Page 138: Receiver/Observation Receiver Signal Chain

    LVDS-SSI data port, the output signal is delivered to the based band processor for further processing. The ADRV9001 supports an RF LO range from 30 MHz to 6 GHz. The RF LOs are generated through two internal phase lock loops (PLL) or applied externally to the part.
  • Page 139 Figure 136. ADRV9001 Rx/ORx/Loopback Diagram The ADRV9001 also uses the three loopback paths internally for two major purposes: transmitter initial calibrations and transmitter tracking calibrations, including the integrated digital predistortion (DPD) operation. Transmitter initial calibrations configure the device properly based on the system configurations during the initialization time.

  • Page 140: Receive Data Chain

    One is the ILB input dedicated for receiving ILB signal. The others are Rx1A/Rx2A and Rx1B/Rx2B inputs. One is configured to receive RF signals and the other to receive ELB signals. The ADRV9001 has an option to select the main receive port (either port A or port B) during initialization.

  • Page 141: Analog Front-End Components

    The attenuator has 256 gain settings providing a receiver attenuation range from 0 to 20 × log(1/256) = -48 dB. Typically, only a subset of this range is used. In the ADRV9001, the current range of the attenuation is from 0 to -34 dB. Calculate the gain of the attenuator by the following equation: 256 −...
  • Page 142 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN The fe_gain_cw[7:0] is an 8-bit control word defined in the receiver gain table. Based on the information from the signal detectors, the gain control algorithm finds the index of this gain table so that the corresponding gain control word at this index is used to calculate the gain at the front-end attenuator.

  • Page 143: Digital Front End Components

    Analog-to-Digital Converter (ADC) As mentioned earlier, the ADRV9001 provides a pair of HP ADCs and LP ADCs to achieve a flexible tradeoff between power consumption and linearity performance. The HP ADC is based on the continuous time delta sigma (CTDS) architecture and is 5 bits wide. The LP ADC is based on the voltage-controlled oscillator (VCO) architecture and is 16 bits wide.
  • Page 144 DC Offset The ADRV9001 receiver supports both IF and ZIF down conversions. The source of the DC offset is mainly from the receiver LO leakage caused by the finite isolation between the LO and RF ports of a mixer, which is typical for silicon-based ICs. It generates a high DC component at the center of the desired signal band, especially for ZIF operation.
  • Page 145 I/Q sinusoid mismatch in both gain and phase, while FDE is mainly caused by the inconsistent filter responses. Because the ADRV9001 supports both the NB and WB modes, NBQEC and WBQEC algorithms are developed accordingly to handle quadrature errors in these two modes effectively.

  • Page 146: Receive Data Chain Api Programming

    RECEIVE DATA CHAIN API PROGRAMMING There is a set of receiver data chain APIs to interact with the ADRV9001 device receive datapath. Some of them are briefly discussed in the previous sections. This set of APIs is classified into three categories: Receiver Gain, Interface Gain, and Miscellaneous APIs, as shown in...
  • Page 147 Reference Manual ADRV9001 RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN Table 60. A List of Interface Gain APIs (Continued) Receiver Interface Gain API Function Name Description adi_adrv9001_Rx_InterfaceGain_Get Gets the receiver interface gain for the given receiver channel. adi_adrv9001_Rx_DecimatedPower_Get Gets the decimated power at configurable locations for the specified channel.

  • Page 148: Transmitter/Receiver/Observation Receiver Signal Chain Calibrations

    Note that the receiver initial calibrations must also be performed on loopback paths to prepare for transmitter initial and tracking calibrations. To successfully perform all the initial calibrations, configure the ADRV9001 device properly. It is fully controlled by the ADRV9001 ARM.
  • Page 149 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS an appropriate level of isolation from the ADRV9001 transmitter output to the antenna to make sure the test tones are not transmitted by the system. Disable the power amplifier during the transmitter initial calibration to achieve this isolation.
  • Page 150 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS ADI_ADRV9001_INIT_CAL_SYSTEM_ALL = 0x00C00000, } adi_adrv9001_InitCalibrations_e The following enumerator type defines the operating modes for initial calibrations. typedef enum adi_adrv9001_InitCalMode ADI_ADRV9001_INIT_CAL_MODE_ALL, ADI_ADRV9001_INIT_CAL_MODE_SYSTEM_AND_RX, ADI_ADRV9001_INIT_CAL_MODE_LOOPBACK_AND_TX, ADI_ADRV9001_INIT_CAL_MODE_ELB_ONLY }adi_adrv9001_InitCalMode_e; ADI_ADRV9001_INIT_CAL_MODE_ALL runs all the selected initial calibrations, including both receiver (non-loopback and loopback paths) and transmitter initial calibrations.
  • Page 151 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 62. Initial Calibration Mask Bit Assignments (Continued) Bits Corresponding Enum Calibration Description profiles, gain indices and frequency regions, and so on. Perform the calibration only on a single channel. ADI_ADRV9001_INIT_CAL_TX_DAC Tx DAC Initial Calibrates the DAC for the required profile bandwidth.
  • Page 152 In this section, high level block diagrams show the device configurations and external system requirements for some transmitter initial calibrations. In all the diagrams, grayed-out lines and blocks are not active in the calibration. Note that as the ADRV9001 ARM performs each of the calibrations, it configures the ADRV9001 device per the following diagrams, with respect to enabling/disabling paths, and so on.
  • Page 153 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Among nine transmitter initial calibrations, except for TX_DAC, all other eight calibrations require to insert the tone/wideband signal into the transmitter datapath from an internal signal generator. Therefore, the internal microprocessor disables the data port to avoid interference. Some...
  • Page 154 Figure 143 shows the high level block diagram of initial transmit calibrations using internal signal generation and ELB1. Note that the ELB1 Initial calibration is a reserved function and the ADRV9001 does not support it. analog.com Rev. 0 | 154 of 351...
  • Page 155 In all the diagrams, grayed-out lines and blocks are not active in the calibration. The blue blocks are related to calibrations. Note that the ADRV9001 ARM performs each of the calibrations. It configures the ADRV9001 device per the diagrams, with respect to enabling/disabling paths, and so on.
  • Page 156 145, the data port is disabled to avoid sending data to the baseband processor. The ADRV9001 ARM controls this without user interaction. Except for the RX_RF_DC_OFFSET calibration, all other digital domain calibration algorithms must be injected with calibration tones generated by the calibration PLL and these must be injected internally at the receiver input.
  • Page 157 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 146. Tx LO Leakage Performance When LO Change = 100MHz with Full Init Cals, Min Init Cals and No Init Cals Figure 147. Tx Image Rejection Performance When LO Change = 100MHz with Full Init Cals, Min Init Cals and No Init Cals Table 65.
  • Page 158 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 65. Initial Calibration Comparison Summary (Continued) Bits Enum User Override Run at Signal Used by External Dependent on Which Init Cals Rerun after LO Capability Boot Calibration Termination is Run First...

  • Page 159: Tracking Calibrations

    RSSI tracking calibration ► The ADRV9001 internal microprocessor fully controls all the tracking calibrations. Therefore, there is no need for user interactions. Tracking Calibrations API Programming The ADRV9001 internal microprocessor in the device schedules/performs tracking calibrations to optimize the performance during its operation.
  • Page 160 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS ADI_ADRV9001_TRACKING_CAL_TX_LB_PD = 0x00000004, ADI_ADRV9001_TRACKING_CAL_TX_DPD_CLGC = 0x00000010, /* Bit 6-7: Not used (Reserved for future purpose) */ ADI_ADRV9001_TRACKING_CAL_RX_HD2 = 0x00000100, ADI_ADRV9001_TRACKING_CAL_RX_QEC_WBPOLY = 0x00000200, /* Bit 10-11: Not used (Reserved for future purpose) */...
  • Page 161 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Table 66. Tracking Calibration Mask Bit Assignments (Continued) Bits Corresponding Enum Calibration Description ADI_ADRV9001_TRACKING_CAL_ORX_QEC_WBPOLY Corrects ORx frequency dependent quadrature error for WB ORx QEC applications. WB Tracking Cali- bration Reserved Reserved Reserved...
  • Page 162 Reference Manual ADRV9001 TRANSMITTER/RECEIVER/OBSERVATION RECEIVER SIGNAL CHAIN CALIBRATIONS Figure 149. Tracking Tx/Rx Calibration Configuration Through TES When an automated TDD configuration is used based on the TDD frame length, some of the tracking calibrations are automatically disabled in TES if the Rx/Tx frame length is less than 1 ms. If the receiver frame is less than 1 ms, RX_HD2, and RX_QEC_WBPOLY are disabled.

  • Page 163: Receiver Gain Control

    RECEIVER GAIN CONTROL The ADRV9001 receivers feature automatic and manual gain control modes for flexible gain control in a wide array of applications. It controls the gain at various stages of the receiver datapath to avoid overloading during the onset of a strong interferer. In addition, it ensures that the receiver digital output data is representative of the root mean square (RMS) power of the receiver input signal so that any internal front-end gain changes to avoid overloading are transparent to the baseband processor.

  • Page 164: Receiver Datapath

    The receivers have front-end attenuators before the mixer stage, which are used to attenuate the signal in the analog domain to ensure the signal does not overload the receiver chain. Note: The ADRV9001 provides about 20dB gain so the front end gain attenuator further attenuates the signal from that level.
  • Page 165 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 150. Rx Datapath and Gain Control Blocks In this gain table, each row provides a unique combination of six fields, including front-end attenuator, TIA control, ADC control, external gain control, phase offset, and digital gain/attenuator. Among them, the TIA control that sets the TIA gain, ADC control that sets the ADC gain, and phase offset that compensates for the phase discontinuity during gain change are reserved for future use.
  • Page 166 The gain table maintains a gain step of 0.5 dB between adjacent gain indices, and it assumes that the LNA step sizes are accurate. Create the new receiver gain table first assuming the max LNA gain (0 dB) until the ADRV9001 front-end attenuator “runs out of” attenuation.
  • Page 167 It is recommended to use the external LNA gain control based on the default Rx gain table, as shown in the above example. However, the ADRV9001 allows to define the minimum gain index in the default Rx gain table (for example, set the minimum gain index to be 211 instead of 195) to accommodate the gain control requirements in the applications.

  • Page 168: Gain Control Modes

    30 dB attenuation. The digital gain specified in the gain table is only used for gain correction. In addition, only manual gain control is supported. Note that the ADRV9001 also uses the ORx gain table internally for initial and tracking calibrations (see...
  • Page 169 Reference Manual ADRV9001 RECEIVER GAIN CONTROL underrange condition occurs, the AGC increases the gain (gain recovery). The AGC stable state (where it does not adjust gain) occurs when neither an underrange nor overrange condition occurs. Each overrange/underrange condition has its own attack and recovery gain step, as shown in Table Table 72.
  • Page 170 Reference Manual ADRV9001 RECEIVER GAIN CONTROL It is possible to enable a fast attack mode, whereby the AGC is instructed to reduce gain immediately when an overrange condition occurs instead of waiting until the next expiry of the gain update counter using changeGainIfThreshHigh. This parameter has independent controls for the APD and HB detectors.
  • Page 171 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 154. AGC Operation with HB Detector in Fast Recovery Mode It is highly recommended that the apdHighThresh and hbHighThresh are set to an equivalent dBFS value. Likewise, it is highly recommended that the apdLowThresh and the hbUnderRangeHighThresh are set to equivalent values. This equivalence is approximate, as these thresholds have unique threshold settings and are not exactly equal.
  • Page 172 Reference Manual ADRV9001 RECEIVER GAIN CONTROL configured to be close to the same value of dBFS, but assuming some small difference between the thresholds, then as soon as apdLowThresh is exceeded, recovery no longer occurs. The reverse is not true. hbUnderRangeHighThresh does not prevent the gain recovery towards the apdLowThresh.
  • Page 173 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 156 shows the operation of the AGC when using the power detector. Considering the power detected in isolation from the peak detectors, the AGC does not modify the gain when the signal level is between overRangeLowPowerThresh and underRangeHighPowerThresh.
  • Page 174 Reference Manual ADRV9001 RECEIVER GAIN CONTROL With power detection, the gain change can only happen at the expiration of the gain update counter, which is typically set in the order of hundreds of microseconds or milliseconds. However, power detectors are usually more stable and unlikely to cause frequent gain changes. In addition, it can provide tighter control of the signal level by using a set of inner and outer thresholds compared to the peak detector.

  • Page 175: Gain Control Detectors

    Reference Manual ADRV9001 RECEIVER GAIN CONTROL consecutive DGPIO pins should always be configured as a pair to retrieve two consecutive bitfields (Bit 0 and Bit 1 or Bit 2 and Bit 3 in both modes). The following enum type defines the DGPIO pin selection.
  • Page 176 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 158. Analog Peak Detector Thresholds There are two APD thresholds, as shown in Figure 158. These thresholds are contained in the agcPeak API structure, apdHighThresh, and apdLowThresh, respectively. The thresholds are typically considered relative to the full scale voltage of the ADC, which is 850 mV peak. The mV setting of the APD thresholds is determined using the following equations.
  • Page 177 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Half-Band Peak Detector The HB peak detector is located in the digital domain at the output of the HB filtering block. It can, therefore, also be referred to as the decimated data overload detector because it works on decimated data. Like the APD detector, it functions by comparing the signal level to programmable thresholds.
  • Page 178 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Each threshold has an associated counter such that an overrange condition is not flagged until the threshold is exceeded this amount of times in a gain update period. Table 80. Counters for HB Overrange and Underrange Conditions...

  • Page 179: Agc Clock And Gain Block Timing

    AGC CLOCK AND GAIN BLOCK TIMING The AGC clock drives the AGC state machine. In the ADRV9001 device, the default AGC clock (to support a set of standard sample rates) is at 184.32 MHz. When an arbitrary sample rate is adopted in the receiver, the AGC clock varies.

  • Page 180: Analog Gain Control Api Programming

    Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 161. Immediate Gain Attack Causing Delayed Gain Recovery To prevent this happening and to maintain a perfectly periodic gain recovery event, the gain attacks are prevented from happening towards the end of the gain update counter state, as shown in Figure 160.
  • Page 181 Reference Manual ADRV9001 RECEIVER GAIN CONTROL If selecting the MGC mode, as discussed, manually control the gain through API commands or DGPIO pins. In the API command mode, select a gain index in the gain table through the API function adi_ADRV9001_Rx_Gain_Set(). The API function adi_ADRV9001_Rx_Gain_Get() can read back the gain index selected for a channel.
  • Page 182 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 163. Member Listing of adi_adrv9001_GainControlCfg_t Data Structure Table 81. adi_adrv9001_GainControlCfg_t Structure Definition Parameter Description Min Value Max Value Default Value peakWaitTime Number of gain control clock cycles to wait before enabling peak detectors after a gain change.
  • Page 183 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 81. adi_adrv9001_GainControlCfg_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value count is exceeded on either the APD or HB detector.1: Gain changes occur immediately when initiated by HB. Gain changes initiated by the APD wait for the gain update to expire.2: Gain changes occur immediately when...
  • Page 184 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 82. adi_adrv9001_PowerDetector_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value applicable in TDD modes. This parameter sets the duration of this power measurement. A value of 0 causes the power measurement to run until the next gain update counter expiry.
  • Page 185 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 83. adi_adrv9001_PeakDetector_t Structure Definition (Continued) Parameter Description Min Value Max Value Default Value not occurring. In the power AGC mode, this threshold prevents further gain increases if the lowThreshPreventGainInc bit is set. apdUpperThreshPeakExceededCount Sets number of peaks to detect above apdHighThresh to cause an APD high overrange event.
  • Page 186 External LNA settling delay There is a set of receiver gain control APIs to interact with the ADRV9001 device. The previous sections mention some of them. Table 85 summarizes the list of API functions with a brief description for each one. Refer to the Doxygen document for more up-to-date information and detailed descriptions.

  • Page 187: Digital Gain Control And Interface Gain (Slicer)

    Reference Manual ADRV9001 RECEIVER GAIN CONTROL Table 85. A List of Rx Gain Control APIs Rx Gain API Function Name Description adi_adrv9001_Rx_GainControl_Mode_Set Configures the Rx gain control mode for a specific channel. adi_adrv9001_Rx_GainControl_Mode_Get Retrieves the currently configured Rx gain control mode.
  • Page 188 Reference Manual ADRV9001 RECEIVER GAIN CONTROL some extra fields, which are 1 bit of slicer gain or AGC gain change indicator and one of the following: zeros, interface gain, or AGC gain index. For more details, see the Data Interface section.
  • Page 189 Reference Manual ADRV9001 RECEIVER GAIN CONTROL applied. The interface gain is determined by RSSI. If the power level is too high, the slicer shifts the signal properly before sending it to the data port to avoid saturation. Let us look at a slicer example that considers three different input signal power levels. The power level 1 fits a data length of 16 bit-width. Power level 2 is 0 dB to 6 dB higher than power level 1, which increases the bit-width by 1.

  • Page 190: Digital Gain Control And Interface Gain Api Programming

    Select the gain from one of the 10 options. In the internal (automatic) mode, the ADRV9001 allows to notify an interface gain it wants to seed using the API adi_adrv9001_Rx_Interface- Gain_SeedGain_Set(). Then, by using the rising edge of an assigned GPIO pin, the interface gain is applied to the Rx output signal. After that, the automatic interface gain algorithm continues.

  • Page 191: Usage Recommendations

    AGC mode is configured when the Gain Control Mode is selected as Automatic. When the Gain Control Mode is selected as Manual Pin or Manual SPI, it further enables the ADRV9001 internal signal detectors in either the Peak Only or Peak and Power mode. By configuring the GPIO pins, the user can retrieve the signal detector status, which can be used to control the receiver gain in the Manual mode.
  • Page 192 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 167. TES Configuration for Rx Gain Control Mode and Signal Detector Operation Mode After configuring the Gain Control Mode and Detection Mode, further configure the interface gain, signal detection parameters, and manual control parameters under the Gain Control tab in the TES, as shown in...
  • Page 193 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 168. TES Configuration for Rx Interface Gain analog.com Rev. 0 | 193 of 351...
  • Page 194 Reference Manual ADRV9001 RECEIVER GAIN CONTROL Figure 169. TES Configuration for Signal Detection Parameters Figure 170. TES Configuration for Manual Control Mode Parameters After finishing all the configurations, start the receive operations and observe the receiver gain changes. It is recommended to start from the default settings and change the parameters one by one as needed.
  • Page 195 Reference Manual ADRV9001 RECEIVER GAIN CONTROL When the receiver gain control is not working as expected, perform the following simple self-debugging. Check if the gain control mode is set as AGC or MGC. ► Check if the MAX and MIN index are set properly. When set improperly, the gain control capability can be significantly impacted.

  • Page 196: Receiver Demodulator

    The ADRV9001 receiver narrowband demodulator subsystem, denoted by rxnbdem, is the digital baseband back-end partition of the ADRV9001 receiver channel. Note that the narrowband is commonly used in wireless communication systems. If the channel spacing (also known as channel bandwidth) is 1 MHz or less, it is known as a "narrowband system," otherwise it is called a "wideband system."...
  • Page 197 Reference Manual ADRV9001 RECEIVER DEMODULATOR Carrier Frequency Corrector (CFC) The carrier frequency corrector (CFC) in rxnbdem removes the carrier frequency offset. This module can be bypassed. In a communication system, the desired signal is transmitted by the transmitter at RF over the air. As the clock reference at the transmitter and receiver are independent, this can result in the RF carrier frequency offset between the transmitter and the receiver.
  • Page 198 Reference Manual ADRV9001 RECEIVER DEMODULATOR The receiver programmable FIR supports up to 128 taps. Each tap is 24 bits in width with the signed bit included. Four sets of customized FIR profiles can be stored at the initialization phase. One of the four stored FIR profiles can be switched to load on the fly under the control of the BBIC.
  • Page 199 Reference Manual ADRV9001 RECEIVER DEMODULATOR j2πf t n A × e ,   n = 0, 1, 2, . . . where: A is the signal magnitude. is the tone frequency. is the sampling frequency. The output of the frequency discriminator (FD) is D × 2f...

  • Page 200: Normal Iq Output Mode

    Note: The current ADRV9001 software release does not support the resampler configuration. Round Module The round module in rxnbdem maps the ADRV9001 internal data path bit-width to the receiver SSI output. This module can be bypassed if the IQ-22bit mode is chosen.

  • Page 201: Application Programming Interface (Api) Programming

    ADRV9001 RECEIVER DEMODULATOR hardware block. Cooperating with other hardware blocks, such as the CFC/DDC, programmable FIR filters, and so on, the ADRV9001 receiver narrowband demodulator can perform frequency-shift key (FSK) and FM demodulation under the control of the BBIC. Figure 179. Rxnbdem in Frequency Deviation Output Mode The FSK/FM demodulation can cover these standards: Analog FM with 12.5 kHz channel bandwidth...
  • Page 202 PFIR pointers are NULL. The ADRV9001 performs the PFIR coefficients switch for all channels that have new coefficients prepared and waiting when the API command adi_adrv9001_arm_Profile_Switch() is called. If the ADRV9001 is in a PRIMED state, the new coefficients take effect on the subsequent transition to RF_ENABLED.

  • Page 203: Power Saving And Monitor Mode

    DMR. The ADRV9001 defines five extra power-down modes that provide low to high power saving but short to long recovery time, and the details are introduced in the following section.

  • Page 204: Power-Down/Up Channel In Calibrated State

    Power-down mode 4 powers down clock PLL and system LDOs related to TX/RX channels in addition to mode 3 power down. ► Power-down mode 5 powers down almost the whole ADRV9001 chip, including ARM and memory, except for some wake-up circuits. ►...
  • Page 205 Reference Manual ADRV9001 POWER SAVING AND MONITOR MODE There are two power-saving choices that can be applied for various TDD interframe scenarios: channel power saving (CPS) and system power saving (SPS). Configure either or both options according to the system specifications.
  • Page 206 Another option is to power down more by using SPS if the dark gray area is very long. Set the power-down mode 3 to 5 to power down most of the ADRV9001 components to save power and wake them up by the DGPIO falling edge early enough before the transmitter enable rising edge.

  • Page 207: Monitor Mode

    (specified by a DGPIO) to move the ADRV9001 into the monitor mode, and the baseband processor itself can go into a sleep state until it is woken up by the ADRV9001 or other system interrupt. During the monitor mode, the ADRV9001 fully controls itself to perform the sleep-detection cycling.
  • Page 208 The ADRV9001 can buffer the latest incoming data in the monitor mode “detecting" cycle. Then, once a valid incoming signal is detected, and the ADRV9001 wakes up the baseband processor, it can send out the buffered receiver data to the baseband processor. This procedure ensures the baseband processor does not miss the valid incoming signal when it is in the sleep state.

  • Page 209: Digital Predistortion (Dpd)

    ADRV9001 DPD FUNCTION The ADRV9001 device provides a fully integrated DPD function that supports both narrowband and wideband applications. It is a hardware/soft- ware combined solution that linearizes the PA by predistorting the digital transmit signal with the inverse of the PA’s nonlinear characteristics.

  • Page 210: Adrv9001 Dpd Supported Waveforms

    DIGITAL PREDISTORTION (DPD) In the ADRV9001 device, DPD is considered one of the transmitter tracking calibrations. It is a real-time signal processing with iterative updates to account for hardware variations such as temperature and power level changes. Similar to other transmitter tracking calibrations, it requires a loopback path from the transmitter to the observation receiver (ORx) to perform the calibration.

  • Page 211: Dpd With Frequency Hopping (Fh)

    Multicarrier Multicarrier Multicarrier Multicarrier Note: The ADRV9001 DPD can also be enabled for the LTE 40MHz profile with a slightly degraded performance, due to the limited DPD observation bandwidth. Table 89 Table 90 show that the multicarrier TETRA2 has a PAR between 9.6 dB to 11.2 dB, and the multicarrier LTE signal typically has a PAR of about 11dB.

  • Page 212: Closed Loop Gain Control (Clgc)

    CLOSED LOOP GAIN CONTROL (CLGC) The ADRV9001 provides CLGC as one of the transmit tracking calibration algorithms. The sole purpose of CLGC is to maintain a fixed gain between the PA output and transmit digital input amplitude. The primary source of gain variation comes from the changes in the gain of the PA, which can vary due to transistor temperature change in response to power output in the short term, RF carrier frequency change within the bandwidth of the amplifier, and slow hardware degradation in the long term.

  • Page 213: Dpd/Clgc Configuration

    CLGC while DPD is active. As the first step of CLGC, set up a target transmit gain. The target transmit gain can be measured through the ADRV9001 using the “CLGC Loop Open” method. The detailed steps of measuring the target gain are discussed later. After the measurement, the ADRV9001 provides an unfiltered and filtered transmit gain value.
  • Page 214 Always choose “4.” ADI_ADRV9001_DPD_MODEL_0 = 0 ADI_ADRV9001_DPD_MODEL_1 = 1 ADI_ADRV9001_DPD_MODEL_3 = 3 ADI_ADRV9001_DPD_MODEL_4 = 4 Model 4 is the ADRV9001 model. changeModelTapOrders bool Sets “TRUE” to use the model tap orders defined FALSE The default model tap order for by “modelOrdersForEachTap”.
  • Page 215 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) enable, clgcEnable The “enable” parameter places the “DPD Actuator” on the datapath of the specified channel to prepare for DPD operation. The “clgcEnable” parameter enables the CLGC functionality. Do this through TES under the “Advanced Features” tab, as shown in Figure 191.
  • Page 216 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 193. TES Configuration for External Loopback with External Power Amplifier amplifierType Currently, set the PA type to ADI_ADRV9001_DPD_AMPLIFIER_DEFAULT if DPD is enabled. The default PA type refers to both the MOS and GaN types of PA.
  • Page 217 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Figure 194. ADRV9001 DPD Model 4 LUT Configuration Figure 194 shows that d(t) is the raw complex transmit signal before predistortion. Its amplitude is the basis used by the DPD actuator to predistort the d(t) through its LUT. The LUT consists of four taps calculated with precomputed DPD coefficients α, as shown here:...
  • Page 218 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Configure the changeModelTapOrders and modelOrdersForEachTap through TES, as shown in 0x7F, B[2] = 0x07 and B[3] = 0x06. Note: Tap 0 and 2 must always be the same. For simplicity, the GUI uses X to represent d n − l...
  • Page 219 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) bool useSpecialFrame; bool resetLuts; uint32_t timeFilterCoefficient; uint32_t dpdSamplingRate_Hz; uint8_t clgcLoopOpen; int32_t clgcGainTarget_HundredthdB; uint32_t clgcFilterAlpha; int32_t clgcLastGain_HundredthdB; int32_t clgcFilteredGain_HundredthdB; uint32_t captureDelay_us; } adi_adrv9001_DpdCfg_t Table 94 briefly summarizes all the DPD/CLGC post initial calibration parameters described in the data structure.
  • Page 220 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) Table 94. DPD/CLGC Post Initial Calibration Parameters (Continued) Parameter Type Description Default Note dpdSamplingRate_Hz uint32_t Sampling rate in Hz for the DPD Read only. No effect on actuator and capture. DPD configuration. clgcLoopOpen uint8_t Open or close the gain loop.
  • Page 221 Once the target gain is set, set it to 0 to close the loop and start the CLGC operation. clgcGainTarget_HundredthdB Configure this parameter to notify the ADRV9001 about the gain target for CLGC with an accuracy of a hundredth of a dB. analog.com...

  • Page 222: Board Configuration

    ADRV9001 transmit output to the ORx input. Measure this delay and provide it to the ADRV9001 before initial calibration. Then use the measured delay to compensate for the delay between x(t) and y(t).

  • Page 223: Save And Load Dpd Coefficients From Last Transmission

    SAVE AND LOAD DPD COEFFICIENTS FROM LAST TRANSMISSION The ADRV9001 DPD also allows to save and load DPD coefficients from the last transmission. Therefore, the DPD can either start from scratch (unity coefficients) or a set of known coefficients. This is a very useful option to reach convergence quickly under a similar transmit operation condition.

  • Page 224: Dpd/Clgc Api Programming

    Without filtering those harmonics, the DPD performance can be impacted. The step attenuators external to the ADRV9001 evaluation board are optional. Note: It is important to set up the external loopback path before operating the integrated DPD. To...
  • Page 225 Tuning the Model Tap Order DPD can be considered an adaptive filter modeled according to the behavior of the PA. The ADRV9001 default model (model 4) consists of four taps. Each tap consists of a series of polynomial terms to fit the nonlinear behavior due to compression at higher output power. The order of polynomial terms is determined by intermodulation falling closer to the carrier spectrum.
  • Page 226 Reference Manual ADRV9001 DIGITAL PREDISTORTION (DPD) The side taps: There are two side taps on each side of the main taps. They are memory terms that compensate for frequency-dependent distortion in the frequency domain and time misalignment between the transmit and receive captured data. The side taps have the same number of polynomial terms, and each side tap has about half of the number of polynomial terms of the main tap.

  • Page 227: Measuring The Clgc Target Gain

    203. The measurement is smoother when a bigger 'α' is used. By default, it is set as 0.75. 10. By determining the final gain target based on the “CLGC last gain” and “CLGC filtered gain” provided by the ADRV9001, configure “CLGC Gain Target”, as shown in the...

  • Page 228: Dynamic Profile Switching (Dps)

    PFIR coefficients or providing a set of custom PFIR coefficients. The ADRV9001 is first calibrated with the main profile as in the regular operation mode without DPS. Then, it is further calibrated for all the dynamic profiles using the API function adi_adrv9001_cals_Dynamic_profiles_calibrate().

  • Page 229: Performing Dps On The Fly

    BBIC, the ADRV9001 starts to perform switching by applying the new profile and PFIR coefficients the BBIC set earlier, and it does not respond to any signals on the Tx_enable and Rx_enable pins. The ADRV9001 takes about 50 µs to complete the switch. After that, the BBIC can move the channels from the “Primed”...

  • Page 230: Dps Api Programming

    Sends the next dynamic profile to the ADRV9001 and waits for it to process when profile switching is performed. adi_adrv9001_arm_NextPfir_Set Sends a bank of PFIR coefficients to the ADRV9001 and waits for it to process when profile switching is performed. adi_adrv9001_arm_Profile_Switch Requests the ADRV9001 to perform dynamic profile switching.

  • Page 231: Dps Operations In Tes

    SSI rate is the highest rate of all dynamic profiles. ► ADRV9001 operates in the frequency hopping or DPS mode, never both. ► DPS OPERATIONS IN TES The TES provides an interface to experiment with DPS. The user can only choose six profiles in the TES. So, the user must configure a profile with the sampling rate no less than 32 MSPS under the “Device Configuration”...
  • Page 232 Reference Manual ADRV9001 DYNAMIC PROFILE SWITCHING (DPS) Figure 209. Performing DPS in TES analog.com Rev. 0 | 232 of 351...

  • Page 233: Power Amplifier Ramp Control

    The integrated AuxDACs, AuxADCs, and GPIOs in ADRV9001 provide sufficient monitoring and controlling channels. ► A fully digital hardware control loop in the ADRV9001 offers high controlling precision to overcome all sorts of non-ideal facts in the loop. ► The integrated ARM core in the ADRV9001 has the intelligence to protect and control the power amplifier. This intelligence includes ►...

  • Page 234: Power Amplifier Close Loop Ramp Control

    ADRV9001 power amplifier close-loop ramp control. Figure 212. Power Amplifier Close Loop Ramp Control with ADRV9001 AuxDAC/AuxADC Amplifying and Buffering Circuits In the open-loop control mode, the look-up table (LUT) stores the AuxDAC words, but in the close-loop control mode, the LUT stores the expectation of the AuxADC inputs vector.

  • Page 235: General-Purpose Input/Output (Gpio) And Interrupt Configuration

    The digital and analog GPIO pins can be used as real-time status signals that provide device status information from the ADRV9001 to the baseband processor when the GPIO pins are configured as outputs with respect to the ADRV9001. When set as inputs, the GPIO pins can be used as real-time control signals that can alter the device's state.

  • Page 236: Gpio Operation

    GPIO OPERATION Set each digital GPIO pin to either the input or output mode. The input mode allows the baseband processor to drive pins on the ADRV9001 to execute specific tasks. The output mode allows the ADRV9001 to output various control or status signals to the baseband processor.
  • Page 237 Power Amplifier Ramp Control When the power amplifier ramp control function is used in the ADRV9001, an optional digital GPIO pin can be assigned as the “power amplifier ramp control enable” functionality driven by the baseband processor. The rising edge of power amplifier ramp control enable with programmable delay acts as the ramp up trigger signal, and the falling edge of power amplifier ramp enable with optional programmable delay as the ramp down trigger signal.
  • Page 238 Control Out Mux Control out mux (monitor out) allows status signals within the ADRV9001 to be output to digital GPIOs, such as the AGC mode of the gain change flag, gain index can be mapped to the DGPIO for BBIC observation by the API adi_adrv9001_Rx_GainIndex_Gpio_Configure().

  • Page 239: Analog Gpio Operation

    The ADRV9001 AGPIO output can control the external LNA gain. Each channel has two AGPIO control signals and achieves control of up to four external LNA gain steps. adi_adrv9001_Rx_ExternalLna_Configure() enables and configures the external LNA gain control.

  • Page 240: Interrupt

    INTERRUPT The ADRV9001 features the general-purpose interrupt output pin (GP_INT). The GP_INT pin can alert the baseband processor that an important event or error regarding the device operation occurred. These events include PLL locking, stream processor errors, ARM exceptions, and so on.

  • Page 241: Auxiliary Converters And Temperature Sensor

    These features are included to simplify control tasks and reduce pin count requirements on the baseband processor by offloading these tasks to the ADRV9001. An example usage of the auxiliary converters includes static voltage measurements performed by the AuxADC and flexible voltage control performed by the AuxDAC.

  • Page 242: Auxiliary Analog-To-Digital Converter (Auxadc)

    AUXILIARY ANALOG‐TO‐DIGITAL CONVERTER (AUXADC) The ADRV9001 has four dedicated AuxADCs: AUXADC_0, AUXADC_1, AUXADC_2, and AUXADC_3. The AuxADC is a 10-bit output delta-sigma converter useful for measuring DC and near-DC signals (<8 kHz). The input voltage range of the AuxADC is 150 mV to 800 mV.

  • Page 243: Temperature Sensor

    AUXILIARY CONVERTERS AND TEMPERATURE SENSOR The AuxADC clock rate is set to 30.72 MHz (or close when the ADRV9001 ARM system clock is changed) to get the best ADC performance. No on-chip calibrations are executed for the AuxADC. The ADC accuracy is limited to the accuracy of the supply reference. A simplified procedure is performed to measure and account for the AuxADC gain and offset errors.

  • Page 244: Rf Port Interface Information

    EXTERNAL LOCAL OSCILLATOR PORTS: LO1± AND LO2± Apply two external LO inputs (LO1 and LO2) to the ADRV9001, and use each external LO signal for any of the two receivers or two transmitters instead of an internally generated LO signal. The AC-coupling interface is needed for both the positive and negative sides of the external LO input pins, which are internally biased.
  • Page 245 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 216. ADRV9001 Transmitter Port Series Equivalent Differential Impedance Figure 217. ADRV9001 Receiver A Port Series Equivalent Differential Impedance analog.com Rev. 0 | 245 of 351...
  • Page 246 Advanced Design System (ADS) Setup Using DAC and SEDZ File Analog Devices supplies the port impedance as an *.s1p series equivalent differential Z (impedance) file. This format allows the simple interface to the advanced design system (ADS) using the data access component (DAC). Term1 is the single-ended input or output and Term2 represents the differential input or output RF port on the ADRV9001.

  • Page 247: General Receiver Port Interface

    Receiver Port A/B Switching The ADRV9001 supports a wide range of RF frequencies from 30 MHz to 6 GHz. However, typical RF baluns do not support all frequencies but only a smaller range. There is a special feature to support switching the receiver A and B ports, which allows to use both of them as receiver channels, and they can be switched at run time depending on the carrier frequency.
  • Page 248 This example uses the receiver port file and laminate file provided by Analog Devices in the design files package. It uses a more detailed ADS setup than mentioned previously.
  • Page 249 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 225. Differential Receiver Port and Laminate Add traces and components to emulate the matching network being implemented with various ADS trace blocks, like MLINE, or with a simulated S parameter block from the layout Gerber files. A simulation of the board files is more accurate to include different trace lengths or curves.

  • Page 250: General Transmitter Bias And Port Interface

    GENERAL TRANSMITTER BIAS AND PORT INTERFACE This section considers the DC biasing of the ADRV9001 transmitter outputs and how to interface with each transmitter port. The ADRV9001 transmitters operate over a range of frequencies. Each differential output side draws approximately 100mA of DC bias current at full output power.
  • Page 251 RF chokes are used to bias the differential output lines that are AC-coupled into the input of a driver amplifier. ► Transmitter Interface Configurations Figure 230. ADRV9001 RF Transmitter Interface Configuration A Figure 231. ADRV9001 RF Transmitter Interface Configuration B Figure 232. ADRV9001 RF Transmitter Interface Configuration C analog.com...

  • Page 252: Impedance Matching Network Examples

    Additionally, the ADRV9001 provides a built-in Transmitter power ramp-up pattern generator to bring transmit power level in a predetermined way to protect internal devices from sudden voltage spikes, which can happen due to the in-rush current passing through an external DC bias choke inductor.

  • Page 253: Receiver Rf Port Impedance Matching Network

    RX1A± and RX2A± Impedance Matching Network The ADRV9001 evaluation board uses both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high-frequency narrowband baluns, while the backside accommodates the larger DB1627 case-style transformer.
  • Page 254 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 107. RX1A± and RX2A± Impedance Matching Network (Continued) L/C/R 245 L/C/R 247 L/C/R 219 C232 L/C/R L/C/R L/C/R L/C/R L/C/R 246 L/C/R 248 L/C/R 220 R232 Frequency Balun L/C 217 L/C 218...
  • Page 255 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Figure 235. RX1B and RX2B Impedance Matching Networks Table 108. RX1B± and RX2B± Impedance Matching Network L/C/R 249 L/C/R 251 L/C/R 227 C233 L/C/R L/C/R L/C/R 250 L/C/R 252 L/C/R 228 R233 Frequency...

  • Page 256: Receiver Rf Port Impedance Match Measurement Data

    Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 108. RX1B± and RX2B± Impedance Matching Network (Continued) L/C/R 249 L/C/R 251 L/C/R 227 C233 L/C/R L/C/R L/C/R 250 L/C/R 252 L/C/R 228 R233 Frequency Balun L/C 222 L/C 224 L/C/R 237...

  • Page 257: Transmitter Rf Port Impedance Matching Network

    TX1± and TX2± Impedance Matching Network For the transmitter path, the ADRV9001 evaluation board uses both the top and bottom layers of the PCB evaluation platform to accommodate two balun footprints. The 0805 footprint accommodates the high- frequency narrowband baluns while the backside accommodates the larger AT224-1A case style transformer.
  • Page 258 RF PORT INTERFACE INFORMATION The ADRV9001 evaluation board provides two options in providing the DC common-mode bias for the transmitter outputs. For transformers that provide a DC feed pin, use this to bias the transmitter output. For transformers that do not provide a DC feed pin, bias the transmitter outputs to 1.8 V through pull-up inductors.

  • Page 259: Transmitter Rf Port Impedance Match Measurement Data

    Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 109. TX1± and TX2± Impedance Matching Network (Continued) C346/34 C333 L309 C309 L/C/R 312 L339 R367/36 C334 L/C/R L/C/R L/C/R L310 C310 L/C/R 313 C339 C335 Frequency Balun L/C 311 R361 L/C 314...

  • Page 260: External Lo Port Impedance Matching Network

    LO frequency. The method of obtaining a matching network is similar to the receiver and transmitter port matching. Depending on the selected divide ratio of the ADRV9001 external LO input frequency divider SPI register setting, a band of frequency must operate in the external LO matching networks, and the chosen division ratio must derive these correctly.
  • Page 261 1 dB differential amplitude error, 2% duty-cycle error, and less than −50 dBc even order harmonics (primarily second order). The ADRV9001 provides a special mode of operation for external LO in the range from 500 MHz to 1000 MHz. In that region, it is possible to inject external LO that produces RF channel frequency with an x1 multiplier.
  • Page 262 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION For example: For FEXTLO = 500 MHz, the FCHANNEL = 500 MHz For FEXTLO = 1000 MHz, the FCHANNEL = 1000 MHz Figure 243. External LO Impedance Matching Network Table 112. EXTLO1± and EXTLO2± Impedance Matching Network...

  • Page 263: External Lo Impedance Match Measurement Data

    CONNECTION FOR EXTERNAL DEVICE CLOCK (DEV_CLK_IN) The ADRV9001 can accommodate three different types of external clock signals applied at the device clock input pins. Apply a differential LVDS clock signal or a single-ended clipped-sinewave clock signal from a TCXO to the device input pins. Furthermore, connect a crystal to the...
  • Page 264 Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 113. Device Clock Input Interface Modes Description (Continued) Voltage Applied at MODEA Device Clock Input Electrical DEV_CLK_OUT Divider Value Applied to Interface DEV_CLK_IN Signal Note /XTAL (20MHz to 80MHz) with Nominal Gm multi- plier = x2 1.8 V...

  • Page 265: Dev_Clk_In Phase Noise Requirements

    Table 115 (or better) allows the ADRV9001 to deliver data sheet performance. Note that Table 114 provides reference information for the ADRV9001 operating with LTE type standards. Each standard determines its own DEV_CLK phase noise requirements. As an example, Table 115 provides recommendations for the DEV_CLK when the ADRV9001 is intended to operate with LMR type standards.

  • Page 266: Connection For Multichip Synchronization (Mcs) Input

    Reference Manual ADRV9001 RF PORT INTERFACE INFORMATION Table 114. DEV_CLK_IN Phase Noise Requirements for 1dB System PN Degradation Compared to an Ideal DEVICE CLOCK Narrow PLL Loop Bandwidth (Approximately 50 kHz) (Default, Wide PLL Loop Bandwidth (Approximately 300 kHz) (User Configured, Typically <3 GHz)

  • Page 267: Printed Circuit Board Layout Recommendations

    The ADRV9001 is a highly integrated RF agile transceiver with significant signal conditioning integrated onto one chip. Due to the integration complexity of the ADRV9001 and its high pin count, a carefully printed circuit board (PCB) layout is important to optimize performance. This section provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues.

  • Page 268: Fanout And Trace Space Guidelines

    FANOUT AND TRACE SPACE GUIDELINES The ADRV9001 device family uses a 196-pin ball grid array (BGA) 12 mm × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it impractical to route all signals on a single layer. There are RF pins on the outer edges of the ADRV9001 package. This helps in routing the critical signals without a fanout via.

  • Page 269: Component Placement And Routing Priorities

    COMPONENT PLACEMENT AND ROUTING PRIORITIES The ADRV9001 transceiver requires a few external components to function, and the ones needed require careful placement and routing to optimize performance. This section provides a priority order and checklist to properly place and route critical signals and components, as well as those whose location and isolation are not as critical.
  • Page 270 Optimize the ZDIFF to fit a narrower frequency range. It is desirable to design the lines for reasonable coupling (−10 dB to −15 dB) to promote adequate electromagnetic interference (EMI) suppression performance. In most cases, the required board artwork stackup is going to be different than the ADRV9001 evaluation board stackup. Optimization of RF ►...
  • Page 271 Traces are shielded by surrounding ground with vias staggered along the edge of the differential trace pair. This arrangement creates a shielded channel that protects the reference clock from any interference from other signals. Refer to the ADRV9001 evaluation board layout for exact details.
  • Page 272 ADRV9001 at a distance from the ADRV9001. The ferrite bead supplies a trace with a reservoir capacitor connected to it. That trace is then shielded with ground and provides power to the ADRV9001 power pin. Place a 1 µF capacitor near the power-supply pin with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors.
  • Page 273 1.0 V analog ► ► This approach uses some of the ADRV9001 internal LDOs to generate 1.0 V for internal blocks. For the remaining blocks, it expects the 1.0 V to be delivered from an external power source. Figure 257 outlines the power-supply routing recommendations for this architecture.
  • Page 274 ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 257. ADRV9001 Power-Supply Domains with Connection Guidelines, Some Internal LDOs Bypassed, 1.0V Analog Domain Required Place ceramic 4.7 µF bypass capacitors at the VRFVCO2_1P0, VRFVCO1_1P0, VRX2LO_1P0, VRX1LO_1P0, VCLKVCO_1P0, VAUXV- CO_1P0, VCONV_1P0, and VDIG_0P9 pins. Place these capacitors as close as possible to the device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and their bypass capacitors, if at all possible.

  • Page 275: Rf And Data Port Transmission Line Layout

    Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 258. ADRV9001 AuxADC, SPI, Analog GPIO/AuxDAC, MCS±, and Digital GPIO Signal Routing Guidelines RF AND DATA PORT TRANSMISSION LINE LAYOUT RF Line Design Summary The RF line design is a compromise among many variables. Line impedance, line-to-line coupling, and physical size represent the parameters subject to compromise.
  • Page 276 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 259. Receiver Matching Network on ADRV9001 Evaluation Board The circuit in Figure 259 shows the layout topology for the chosen receiver matching network. Note the location and orientation of each component (placement is critical for expected performance). Similarly, the circuit in...
  • Page 277 Transmitter Bias and Port Interface This section considers the DC biasing of the ADRV9001 transmitter outputs and how to interface to each transmitter port. At full output power, each differential output side draws approximately 100 mA of DC bias current. The transmitter outputs are DC biased to a 1.8 V supply voltage using either RF chokes (wire-wound inductors) or a transformer (balun) center tap connection.
  • Page 278 Each transmitter requires approximately 200 mA supplied through an external connection. The PCB layout of the ADRV9001 board allows the use of external chokes to provide 1.8 V power domain to the ADRV9001 outputs. This allows users to try different baluns that do not have a DC center tap pin to supply the bias voltage to the transmitter outputs.
  • Page 279 264. Place the decoupling cap near the transmitter balun as close as possible to the balun’s DC feed pin. Its orientation is perpendicular to the ADRV9001 device so the return current avoids a ground loop with the ground pins surrounding the receiver input. The customer card provides an option to install an RF isolation inductor, which can provide extra isolation between the Tx1 and Tx2 balun supply feeds.
  • Page 280 If selecting the CMOS-SSI mode, single-ended signal lines between the ADRV9001 and BBIC/FPGA must be as short as possible. Also reduce the trace capacitance to minimize the current needed by the ADRV9001 to drive the line. Refer to the ADRV9001 data sheet for details on pin drive capabilities.
  • Page 281 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Table 117. FMC Pinout Mapping Used by ADRV9001 Evaluation Board Schematic Net Name FMC Connector Mappings FPGA_REF_CLK+ G02-FMC_CLK1_M2C_P FPGA_REF_CLK- G03-FMC_CLK1_M2C_N DEV_CLK_OUT H04-FMC_CLK0_M2C_P SM_FAN_TACH H05-FMC_CLK0_M2C_N RX1_DCLK_OUT+ G06-FMC_LA00_CC_P RX1_DCLK_OUT- G07-FMC_LA00_CC_N RX1_STROBE_OUT+ H07-FMC_LA02_P RX1_STROBE_OUT- H08-FMC_LA02_N...

  • Page 282: Isolation Techniques Used On The Adrv9001 Evaluation Card

    ► There are several strategies to reduce the impact of these coupling mechanisms on the ADRV9001 customer evaluation. Open large slots in the ground plane between the RF I/O paths. These discontinuities prevent surface propagation. These structures consist of a combination of slots and square apertures.
  • Page 283 ADRV9001 evaluation card. When using slots, place the ground vias at each end of the slots and along each side. When using square apertures, place at least one single ground via next to each square. These vias are through-hole vias connecting the top to the bottom layer and all layers in between.
  • Page 284 Reference Manual ADRV9001 PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Figure 268. Shielding of Rx Launches Space and align the RF I/O baluns to reduce magnetic coupling from the structures in the balun package. Take care to reduce the crosstalk over shared grounds between baluns. Another precaution is to place and orient the SMA connectors to minimize the connector-to-connector coupling between ports.

  • Page 285: Power-Supply Recommendations

    VDDA_1P0 is not used, this 1.0 V power domain is created internally inside the ADRV9001 using internal LDOs. This power domain supplies voltage to noise sensitive blocks of the ADRV9001. To provide external 1.0 V, ensure very low noise level on this power domain.
  • Page 286 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 119. Power-Supply Pins and Functions Pin No. Type Pin Name Voltage [V] Description A1, A2, A13, ANALOG VSSA Analog supply voltage (V A14, B2 to B5, B10 to B13, C2, C5, C10, C13, D1 to D6, D9 to...
  • Page 287 ► resistor placeholders in series force the use of separate traces to deliver different power domains to the ADRV9001 device. Provides a place in the circuit to monitor and measure the current for debugging. For this case, replace the 0 Ω components or FB with very ►...
  • Page 288 A switch-mode regulator (ADP5056) is used to achieve power efficiency while generating domains that supply the ADRV9001. Remote sensing configuration is used to take into account the voltage drop in filters and ensure power domain accuracy at the ADRV9001 input pins.
  • Page 289 Locate the E3 and C4 elements right at the trace that feeds the particular pin. ► Place the C4 element as the RF capacitor right at each ADRV9001 pin using the rail. For more information about placing these capacitors, ►...

  • Page 290: Power-Supply Configurations

    From the power-supply implementation point of view, the ADRV9001 can work in multiple configurations. This section outlines them in detail. It depends on the final application of the ADRV9001 in the end system that provides the freedom to implement different ways to power the IC.
  • Page 291 Rx1 and Tx1 datapaths and disable the Rx2 and Tx2 datapaths. Once any of the configurations outlined in Figure 273, Figure 274, or Figure 275 is implemented, initialize the ADRV9001 device with the correct initialization settings described in the data structure. analog.com Rev. 0 | 291 of 351...
  • Page 292 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 273. Available Modes for External 1.0V Power Domain and LO Power-Supply Configuration analog.com Rev. 0 | 292 of 351...
  • Page 293 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Figure 274. Power-Supply Modes for Different Number of Active Tx RF IOs analog.com Rev. 0 | 293 of 351...
  • Page 294 In cases where not all RF IOs or other interface pins are used in the end application, follow Table 120 for recommendations on what to do with unused pins. Table 120. Instructions Explaining How to Handle ADRV9001 Unused Pins Pin No. Type Mnemonic...
  • Page 295 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 120. Instructions Explaining How to Handle ADRV9001 Unused Pins (Continued) Pin No. Type Mnemonic Unused Instructions Input VANA1_1P3 Not applicable. Input/Output VANA1_1P0 Not applicable. C11, C12 Input RX1B-, RX1B+ When accidentally enabled, bias voltage is present on these inputs.

  • Page 296: Power Supply Optimization

    Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Table 120. Instructions Explaining How to Handle ADRV9001 Unused Pins (Continued) Pin No. Type Mnemonic Unused Instructions Input TX1_EN Do not connect. Input MODE Connect to VSSA. Output DEV_CLK_OUT Do not connect. Output RX2_IDATA_OUT- Do not connect.
  • Page 297 Reference Manual ADRV9001 POWER-SUPPLY RECOMMENDATIONS Make optimizations in the power supply section to reduce the number of individual rails and filters to save on BOM and space. One possible optimization is the combination of different rails of the same voltage domain. In doing this, it is important to identify the aggressor and victim rails to decide what to combine and what to keep shielded with an FB filter.

  • Page 298: Summary

    SUMMARY The design specification for the ADRV9001 EVB shows the best performance of the part with little to no degradation from the PCB design. The Analog Devices applications engineering team recommends the circuit board layout and power-supply decoupling covered in this document.

  • Page 299: Ldo Configurations

    1 V rails. The new 1 V external power domain is a low-noise supply with a tolerance of ±2.5%. The LDO configurations on the ADRV9001 can affect the overall power consumption. On the ADRV9001 evaluation board, all the internal LDOs are used and they generate the 1 V needed for all the rails.
  • Page 300 ► domain is still required. Apply a high-efficiency power source at the input pin. This mode allows to use higher efficiency power sources to supply the ADRV9001, as opposed to having the power overhead associated with an LDO. Table 123 lists each of the 19 LDOs as well as the constraints to explain when to power on/off, or bypass each LDO.
  • Page 301 Reference Manual ADRV9001 LDO CONFIGURATIONS Table 124. Power-Saving Configuration for Each LDO (Continued) Index Configuration 2 Configuration 1 Configuration 0 GP_LDO_2 RX_2_LO_LDO TX_2_LO_LDO CLK_PLL_SYNTH_LDO CLK_PLL_VCO_LDO CLK_PLL_LP_SYNTH_LDO CLK_PLL_LP_VCO_LDO LO1_PLL_SYNTH_LDO LO1_PLL_VCO_LDO LO2_PLL_SYNTH_LDO LO2_PLL_VCO_LDO AUX_PLL_SYNTH_LDO AUX_PLL_VCO_LDO SRAM_LDO Use the API function adi_adrv9001_powermanagement_Configure() to implement a device driver interface, allowing to set the ldoPowerSa- vingsModes.
  • Page 302 Reference Manual ADRV9001 LDO CONFIGURATIONS the LDO mode. So, pay attention to correctly set the part to reflect the physical implementation. Attention is also needed when bypassing LDOs to make sure that internal circuits are not supplied with incorrect voltage levels.
  • Page 303 Reference Manual ADRV9001 LDO CONFIGURATIONS Figure 281. Tx1/Rx1 External LO Power Solution Now that the hardware configuration is known, determine the LDO configuration and set each LDO to the correct mode. Table 125 outlines the mode needed for each LDO to prevent overvoltage failures or other unwanted errors.
  • Page 304 Reference Manual ADRV9001 LDO CONFIGURATIONS Table 125. Example LDO Modes and Pin Mapping (Continued) Index LDO Mode Output Pin Output Pin Number Comments GP_LDO_2 VANA2_1P0 Powered off, ch2 not required. RX_2_LO_LDO VRX2LO_1P0 Powered off, ch2 not required. TX_2_LO_LDO VTX2LO_1P0 Powered off, ch2 not required.

  • Page 305: Adrv9001 Evaluation System

    The user must have administrative privileges. ► SD Card Imaging To image the SD card properly for use in the Xilinx platform, download the ADRV9001 Disk Imaging Utility and the dotNet Disk Imager. Find ® these on the EngineerZone support forum for the TES GUI &...
  • Page 306 ADRV9001 EVALUATION SYSTEM the ADRV9001 performance. However, as of the date of the current release of this user guide, there are no known incompatibilities with any versions and derivatives of the ZC706. For example, the following versions have been successfully used for evaluation purposes: EK-Z7-ZC706-G and EVAL-TPG-ZYNQ3 Figure 282.
  • Page 307 3. Insert the SD card that comes with the ADRV9001 evaluation kit into the ZYNQ ZC706 evaluation platform SD card slot (J30). 4. On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES) at a +13 dBm power level to the J501 connector ((this signal drives the reference clock into the ADCLK944 clock distribution chip on the board (the Q1/Q1_N pins of the ADCLK944 generate the DEV_CLK for the ADRV9001 and REF_CLK for the Xilinx FPGA on the ZYNQ platform)).
  • Page 308 3. Insert the SD card that came with the ADRV9001 evaluation kit into the ZCU102 evaluation platform SD card slot (J100). 4. On the ADRV9001 evaluation card, provide a device clock (frequency must match the setting selected in the TES) at a +13 dBm power level to the J501 connector ((this signal drives the reference clock into the ADCLK944 clock distribution chip on the board (the Q1/Q1_N pins of the ADCLK944 generates the DEV_CLK for the ADRV9001 and REF_CLK for the Xilinx FPGA)).

  • Page 309: Hardware Operation

    4. To test the receiver on the ADRV9001 evaluation card, use a clean signal generator with low-phase noise to provide an input signal to the selected receiver RF input. Use a shielded RG‑58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.

  • Page 310: Transceiver Evaluation Software

    ADRV9001 EVALUATION SYSTEM 4. To test the receiver on the ADRV9001 evaluation card, use a clean signal generator with low phase noise to provide an input signal to the selected receiver RF input. Use a shielded RG‑58, 50 Ω coaxial cable (1 m or shorter) to connect the signal generator.
  • Page 311 288). Stay with the default location C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software. If this is not possible, install the TES into any other location with write access. Select the shortcut configuration as the last step of the installation process.
  • Page 312 Figure 290 shows an example of the correct connection between a PC and a Xilinx platform with an ADRV9001 daughter card connected to it. In this window, check both the hardware version and all software component versions used by the system in the current TES revision.
  • Page 313 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Supports ADRV9002, ADRV9003, and ADRV9004. ► System ► Supports TDD, FDD and TDM_FDD. ► Under TDD: ► Supports DMR setup. ► Supports Analog FM setup. ► Supports LTE setup. ► Supports Configuration 1, 3, and 4 setup.
  • Page 314 1. Measure the LTE10 profiles to obtain the highest possible measurement accuracy. 2. Measure upon ADRV9001 entering the CALIBRATED state for the first time. Obtain SSI Ref Clock from the transmitter or receiver channel. When using the clock from the transmitter channel, push this to two GPIO pins.
  • Page 315 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 292. Receiver/Observation Receiver Loopback Diagram Figure 293. Extended Gain Table Example analog.com Rev. 0 | 315 of 351...
  • Page 316 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 294. Board Configuration Tab Clocks The Clocks tab (Figure 295) provides access to the settings that determine the device clock configuration. This page allows to: Set the device clock. ► Set the device clock frequency.
  • Page 317 Set the divisor value. b. The TES informs about the external LO frequency to provide to the ADRV9001 transceiver at the external LO input. 6. If Internal LO is used, then select Best Phase Noise or Best Power Saving for the application. Note that the Best Phase Noise option supports only Sub-1 GHz transmitter frequencies.
  • Page 318 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 297. Carriers Configuration Tab (Frequency Hopping) Figure 298. Carriers Configuration Tab (Frequency Hopping Tables) Radio The Radio tab (Figure 299) configures the channel enablement, and transmitter and receiver characteristics. Select the channel control mode (hardware enable signals or API command).
  • Page 319 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Use "Transmit Data Source" to send data from the FPGA or NCO internal signal source. ► Figure 299. Radio Configuration Tab Advanced Features The Advanced Features tab (Figure 300) provides access to the settings that enable a set of advanced features the device supports. This...
  • Page 320 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM This can enable the stream status to be seen on the GPIOs to measure the rise-to-analog-on time. ► Figure 300. Advanced Features Tab Figure 301. Synchronous Transfer Option in the Transmit Tab Note that the evaluation software has the synchronous transfer option. This option allows to begin the transfer of data (through the FPGA DMA) on both channels (Tx1 and Tx2 or Rx1 and Rx2) at the same point in time.
  • Page 321 Receiver and Transmitter Filters The ADRV9001 evaluation software specifies the custom programmable filter for each channel. These filters are up to 128 taps. The custom filter must be in the .csv or .txt file format and the coefficients must be 24-bit signed integers with no carriage returns. The SDK has an example filter .txt file.
  • Page 322 The Rx Overview (Figure 305) and Tx Overview (Figure 306) tabs provide more details on the ADRV9001's selected mode of operation using the Device Configuration tab (Figure 291). Each tab provides the receiver and transmitter datapath overview diagrams. These tabs provide the readback of ADC/DAC sampling frequencies, analog filtering configuration, datapath sampling rate, data port format, mode of operation, and sampling rate.
  • Page 323 Transmit the content of the selected file. The TES comes with some example files. Assuming the default TES installation process, the ► example files are located in C:\Program Files (x86)\Analog Devices\ADRV9002 Transceiver Evaluation Software\Example. Transmit a single-tone, two tones, and zeros. Adjust the digital power of the single- or dual-tone signal as well as the frequency offsets.
  • Page 324 ► Pressing the play symbol moves the ADRV9001 to the transmit state and starts a process where selected data files for the Tx1 and Tx2 are sent to the ADRV9001. The data is then stored on the Xilinx platform motherboard RAM and the RAM pointer loops through the data continuously until Stop is pressed.
  • Page 325 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Change the capture length in number of samples. ► Change the receiver gain level (gain table index). ► Change the receiver interface gain (in four steps). ► Enable/disable the "Baseband DC Rejection" tracking calibration.
  • Page 326 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM | I1 | Q1 | I2 | Q2 When the I and Q column option is selected the data is formatted as follows: Channel 1I | Channel 1Q ----------|----------- | Q1 | Q2 | Q3 | Q4 For receiver frequency deviation, only I samples are shown and all Q samples are 0.
  • Page 327 312) configures the receiver gain control mode per channel. Apply the configuration selected in that tab to the ADRV9001 during initialization. During run time, change the interface gain as well as if the manual mode is enabled, then change the receiver gain.
  • Page 328 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Compensation: It is the process of compensating for the analog attenuation in the device (prior to the ADC) with a corresponding amount of ► digital gain before sending the digital signal to the user. Gain compensation uses the digital gain to effectively undo the analog gain so that the recipient signal from the receiver data stays constant.
  • Page 329 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 313. Transmitter Front End Once the pins are assigned, go to the Transmit tab and start normal playback. Then adjust the transmitter attenuation level using the up and down arrows, and this adjusts the transmitter attenuation value by the specified step size.
  • Page 330 The ADRV9001 supports the automatic time division duplexing (TDD) operation. Send and receive TDD-framed data by configuring this tab (Figure 316). This of course depends on how the system and setup is selected. The ADRV9001 comes with predefined timing configurations by default. However, configure the timing as needed.
  • Page 331 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 316. Automated TDD Configuration Tab Figure 317. Automated TDD Timing Diagram TDD Parameter Table The table auto populates the TES based on the chosen configuration file. Enable Column ► Enable/disable the receiver/transmitter channel.
  • Page 332 Enabling the Tx1 DMA sends data from the FPGA to SSI. Disabling the Tx1 DMA stops sending data from the FPGA to SSI. It works together with the Tx_interface enabling/disabling (accepting data from SSI at the ADRV9001) to provide more flexibility to control what data to transmit.
  • Page 333 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM DMA disabled, Tx_interface enabled: 0s are transmitted. ► DMA enabled, Tx_interface disabled: data in DMA is not transmitted and is lost. ► DMA enabled, Tx_interface enabled: data in DMA is transmitted. ► The following enum defines the Tx1 DMA trigger.
  • Page 334 Auxiliary DAC/ADC The ADRV9001 evaluation software allows to set the Auxiliary ADC/DAC for different control or monitoring purposes. Go to the Auxiliary tab and enable "Aux DAC/ADC". For Aux DACs, specify a DAC code, valued from 0 ~ 4095. This effectively sets the voltage level for that Aux DAC pin.
  • Page 335 Figure 321. IronPython Scripting Window The SDK has examples of IronPython scripts to run API functions that do not appear in the GUI. Find these files in the ADRV9001 Transceiver Evaluation Software\IronPython folder, and load these through the File menu and Load.
  • Page 336 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM External Path Delay Measurement (for DPD) Connect the Tx1 output, through the chosen power amplifier, to the Rx1B input with a cable (add an optional step attenuator to the loop). Configure the TES to indicate there is an external path after the power amplifier in the Board Configuration tab. Enable the DPD from the Advanced Features tab.
  • Page 337 Power/Temperature Monitoring The ADRV9001 evaluation software allows to monitor the power usage of the system. On top, Power/Temp Monitoring shows the detailed voltage, current, and power status of each power domain. It also shows the temperature from an internal temperature sensor.
  • Page 338 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 325. Power / Temperature Monitoring Window Power Savings This option opens a window with radio button options to change the system state for monitor mode. Select the "Monitoring" button to force the state into monitor mode. Similarly select "Detected" to push the state to detected. There are options to toggle monitor mode enable and wake up pins, also options to toggle both channels power saving pins.
  • Page 339 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 327. Timing Diagrams Frequency Hopping Frequency hopping displays the frequency hopping wizard window that assists in setting up the frequency hopping tables in a step-by-step format. For more details, see the Frequency Hopping section.
  • Page 340 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 328. Frequency Hopping Wizard Use this wizard to set up all the frequency hopping tables, starting with Use Case and Timing Constraints. Select the type of Carrier Frequency Strategy from ping pong to dynamic table loading. This dictates how many tables to initialize and how the frequency information is loaded from the table.
  • Page 341 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 329. Interface Gain Seed / Save Log File The Log File button at the top of the GUI shows the logging information of the system. If the PC is connected to the evaluation platform, the log file shows the version numbers for the different components of the system, including the firmware, FPGA, API, and others.
  • Page 342 ADRV9001 EVALUATION SYSTEM Figure 331. Auto Generated Code Options Frequency Hopping TES Examples This section shows three examples to use the TES to achieve frequency hopping for the ADRV9001. For details on the frequency hopping operation, see the Frequency Hopping section.
  • Page 343 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM 4. Specify the "Hop Pin" . By default, set it to "Pin 01". 5. Specify the "Hop Mode". Different profiles have certain modes enabled/disabled. a. "Mux Preprocess" indicates two LOs in use for frequency hopping, and the tables are preprocessed before hopping.
  • Page 344 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 334. Frequency Hopping Executed Sequence 9. Click Program. 10. Upon successful programming, go to the Transmit tab and click Play. A window pops up and indicates the frequency hopping is working in the manual mode.
  • Page 345 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Figure 336. Manual Frequency Hopping Using TES a. The upcoming frame is assigned to the transmitter (first box). b. There should not be any signal coming out of the transmitter. 3. Click Commit Frame-After-Next to Tx and Perform Hop again.
  • Page 346 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Receiver Only The Receiver Only steps are the same as Transmitter Only . The only difference is that instead of clicking Play on the Transmit tab, click Play on the Receive tab. Transceiver The transceiver steps are also very similar, except that click Play on both the Transmit and Receive tabs before operating frequency hopping.
  • Page 347 1. Follow the steps in Example 2 before programming. 2. In the Automated TDD tab, click Enable Automated TDD State Machine for FPGA. 3. The ADRV9001 TES includes several predefined examples in the /Examples folder. analog.com Rev. 0 | 347 of 351...
  • Page 348 Reference Manual ADRV9001 ADRV9001 EVALUATION SYSTEM Receiver Only 1. Select the predefined JSON file DMR_24K_RX_ONLY_FH.json. 2. Hop Pin is set automatically. 3. Go to the Receive tab, set the capture length to the longer value. Here, it is set to 65536.

  • Page 349: Evaluation System Troubleshooting

    An early image is required for all SDK versions previous to 0.13.0. For SDK releases 0.13.0 or later, a new SD card image is required. This is all taken care of with the Analog Devices SD card imaging software. But check if older versions have been used before. The .img files are also now available on the ADRV9001 product page.
  • Page 350 Red LED Constantly On 1. The Xilinx platform generates the power domain for IOs that control the ADRV9001 over the FPGA mezzanine card (FMC) interface. This power domain is called VADJ. For proper operation, voltage on that power domain must not exceed 1.89 V. The SD card provided with the evaluation card ensures that VADJ is properly set.
  • Page 351 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Table of Contents