Analog Devices ADRV9005 Reference Manual page 65

Reference Manual
DATA INTERFACE
Table 25 shows the CMOS SSI electrical specifications. For optimal performance, keep the load capacitance driven by the CMOS outputs to a
minimum. The CMOS output drive strength can be increased to compensate for load capacitance larger than 10 pF to increase the edge rate of
the output signal during the transition period. The maximum load capacitance is 30 pF at an 80 MHz clock data rate.
In the LVDS mode, a 100 Ω differential termination resistor is required for each LVDS pair, which must be located as close to the LVDS receiver
as possible. The ADRV9001 LVDS input circuit has an optional internal 100 Ω termination resistor, which is enabled by default for LSSI.
The ADRV9001 LVDS output circuits do not have internal termination resistors, and the user is expected to implement the appropriate LVDS
termination resistors in the LVDS receiver. The default LVDS output circuit produces 350 mV peak at 1.2 V common-mode level. The output
swing level can be increased to 450 mV for longer trace (currently not supported).
It is recommended to closely match the trace lengths of SSI clock, strobe, data signals into each transmit or receive channel. The ADRV9001
SSI has configurable delay cells on the LVDS/CMOS input and output circuits, which allow small adjustments to the phase relationship between
the strobe/data and clock. The adjustable phase delay cell increments in approximately 90 ps per step in the LVDS mode, and 170 ps per step
in the CMOS mode, up to a maximum of seven steps.
Table 25. CSSI Electrical Specification
Symbol Parameter
VDIGIO_1P8 Interface power supply voltage
V Input voltage high
IH
V Input voltage low
IL
V Output-voltage high
OH
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Figure 31. ADRV9001 SSI I/Os Mapping
Table 26
Min
1.71
VDIGIO_1P8 × 0.65
-0.3
VDIGIO_1P8 − 0.45
shows the LVDS SSI electrical specifications.
Typ Max
1.8 1.89
VDIGIO_1P8 + 0.18
VDIGIO_1P8 × 0.35
VDIGIO_1P8
ADRV9001
Units
V
V
V
V
Rev. A | 65 of 377